| /openbmc/qemu/tests/tcg/s390x/ |
| H A D | shift.c | 6 static uint64_t _name(uint64_t op1, uint64_t op2, uint64_t *cc) \
15 : [op2] "r" (op2) \
26 static uint64_t _insn ## _ ## _offset(uint64_t op1, uint64_t op2, \
42 : [op2] "r" (op2) \
74 uint64_t op2; member
84 .op2 = 0x62e5508ccb4c99fdull,
92 .op2 = 0x5ffcf7465f5cd71full,
100 .op2 = 0x3ddf2f53347d3030ull,
108 .op2 = 0x18d586fab239cbeeull,
116 .op2 = 0x4d193b85bb5cb39bull,
[all …]
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| H A D | exrl-trt.c | 7 char op2[256]; in main() local
15 op2[i] = 0xaa; in main()
17 op2[i] = 0; in main()
30 [op2] "Q" (op2) in main()
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| H A D | exrl-trtr.c | 7 char op2[256]; in main() local
15 op2[i] = 0xbb; in main()
17 op2[i] = 0; in main()
30 [op2] "Q" (op2) in main()
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| H A D | laalg.c | 11 unsigned long cc = 0, op1, op2 = 40, op3 = 2; in main() local
18 , [op2] "+T" (op2) in main()
24 assert(op2 == 42); in main()
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| H A D | csst.c | 13 uint64_t op2 = 0; in main() local
23 [op2] "+m" (op2), in main()
38 if (op2 != parmlist[2]) { in main()
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| H A D | ipm.c | 7 uint32_t op2 = 0x44444444; in main() local
15 [op2] "r" (&op2) in main()
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| H A D | clm.S | 9 clm %r0,6,op2
22 op2: label
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| H A D | icm.S | 9 icm %r0,10,op2
23 op2: label
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| /openbmc/qemu/target/alpha/ |
| H A D | int_helper.c | 90 uint64_t helper_minub8(uint64_t op1, uint64_t op2) in helper_minub8() argument
98 opb = op2 >> (i * 8); in helper_minub8()
105 uint64_t helper_minsb8(uint64_t op1, uint64_t op2) in helper_minsb8() argument
114 opb = op2 >> (i * 8); in helper_minsb8()
121 uint64_t helper_minuw4(uint64_t op1, uint64_t op2) in helper_minuw4() argument
129 opb = op2 >> (i * 16); in helper_minuw4()
136 uint64_t helper_minsw4(uint64_t op1, uint64_t op2) in helper_minsw4() argument
145 opb = op2 >> (i * 16); in helper_minsw4()
152 uint64_t helper_maxub8(uint64_t op1, uint64_t op2) in helper_maxub8() argument
160 opb = op2 >> (i * 8); in helper_maxub8()
[all …]
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| /openbmc/qemu/target/arm/hvf/ |
| H A D | trace-events | 1 …32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x (op0=%d op1…
2 …32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x (op0=%d op…
6 …p1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d op1=%d crn…
7 …1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d op1=%d crn…
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| /openbmc/u-boot/post/lib_powerpc/ |
| H A D | cmp.c | 27 extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2);
33 ulong op2; member
100 cpu_post_exec_12 (code, & res, test->op1, test->op2); in cpu_post_test_cmp()
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| H A D | threex.c | 27 ulong op2);
34 ulong op2; member
177 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_threex()
189 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_threex()
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| H A D | rlwimi.c | 24 ulong op2);
32 uchar op2; member
75 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwimi()
94 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | in cpu_post_test_rlwimi()
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| H A D | rlwnm.c | 24 ulong op2);
31 ulong op2; member
113 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
125 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
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| H A D | three.c | 27 ulong op2);
34 ulong op2; member
207 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
219 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
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| H A D | srawi.c | 30 uchar op2; member
72 ASM_11S(test->cmd, reg1, reg0, test->op2), in cpu_post_test_srawi()
89 ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, in cpu_post_test_srawi()
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| H A D | cmpi.c | 33 ushort op2; member
94 ASM_1IC(test->cmd, test->cr, 3, test->op2), in cpu_post_test_cmpi()
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| H A D | rlwinm.c | 30 uchar op2; member
70 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwinm()
87 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, in cpu_post_test_rlwinm()
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| H A D | string.c | 24 extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2);
25 extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3,
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| H A D | cr.c | 38 extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3);
89 ulong op2; member
313 ASM_12F(test->cmd, test->op3, test->op1, test->op2), in cpu_post_test_cr()
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| /openbmc/u-boot/drivers/bios_emulator/x86emu/ |
| H A D | ops2.c | 58 u8 op2) in x86emuOp2_illegal_op() argument
64 M.x86.R_CS, M.x86.R_IP-2,op2); in x86emuOp2_illegal_op()
145 void x86emuOp2_long_jump(u8 op2) in x86emuOp2_long_jump() argument
152 cond = x86emu_check_jump_condition(op2 & 0xF); in x86emuOp2_long_jump()
167 void x86emuOp2_set_byte(u8 op2) in x86emuOp2_set_byte() argument
176 switch (op2) { in x86emuOp2_set_byte()
263 void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) in x86emuOp2_push_FS() argument
277 void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) in x86emuOp2_pop_FS() argument
291 void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) in x86emuOp2_bt_R() argument
354 void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) in x86emuOp2_shld_IMM() argument
[all …]
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | vec_helper.c | 1184 static uint16_t float16_ceq(float16 op1, float16 op2, float_status *stat) in float16_ceq() argument
1186 return -float16_eq_quiet(op1, op2, stat); in float16_ceq()
1189 static uint32_t float32_ceq(float32 op1, float32 op2, float_status *stat) in float32_ceq() argument
1191 return -float32_eq_quiet(op1, op2, stat); in float32_ceq()
1194 static uint64_t float64_ceq(float64 op1, float64 op2, float_status *stat) in float64_ceq() argument
1196 return -float64_eq_quiet(op1, op2, stat); in float64_ceq()
1199 static uint16_t float16_cge(float16 op1, float16 op2, float_status *stat) in float16_cge() argument
1201 return -float16_le(op2, op1, stat); in float16_cge()
1204 static uint32_t float32_cge(float32 op1, float32 op2, float_status *stat) in float32_cge() argument
1206 return -float32_le(op2, op1, stat); in float32_cge()
[all …]
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| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | parser-helpers.c | 517 HexValue *op2) in gen_bin_cmp() argument
520 HexValue op2_m = *op2; in gen_bin_cmp()
562 HexValue *op2, in gen_simple_op() argument
572 op2->signedness); in gen_simple_op()
575 " = ", op1, imm_imm, op2, ";\n"); in gen_simple_op()
579 "(", res, ", ", op2, ", ", op1, ");\n"); in gen_simple_op()
583 "(", res, ", ", op1, ", ", op2, ");\n"); in gen_simple_op()
587 "(", res, ", ", op1, ", ", op2, ");\n"); in gen_simple_op()
595 HexValue *op2) in gen_sub_op() argument
601 op2->signedness); in gen_sub_op()
[all …]
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| /openbmc/qemu/target/arm/ |
| H A D | cpu-sysregs.h | 14 #define ENCODE_ID_REG(op0, op1, crn, crm, op2) \ argument
19 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
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| /openbmc/qemu/target/tricore/ |
| H A D | translate.c | 446 void(*op2)(TCGv, TCGv, TCGv)) in gen_addsub64_h()
463 (*op2)(temp3, r1_high, r3); in gen_addsub64_h()
467 if (op2 == tcg_gen_add_tl) { in gen_addsub64_h()
2621 void(*op2)(TCGv, TCGv, TCGv)) in gen_bit_2op()
2632 (*op2)(temp1 , ret, temp1); in gen_bit_2op()
3480 uint32_t op2; in decode_sr_system() local
3481 op2 = MASK_OP_SR_OP2(ctx->opcode); in decode_sr_system()
3483 switch (op2) { in decode_sr_system()
3487 gen_compute_branch(ctx, op2, 0, 0, 0, 0); in decode_sr_system()
3506 uint32_t op2; in decode_sr_accu() local
[all …]
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