Searched refs:num_context_banks (Results 1 – 5 of 5) sorted by relevance
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()135 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_mmu500_reset()
607 return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); in arm_smmu_alloc_context_bank()1604 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_smmu_device_reset()1788 smmu->num_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMCB, id); in arm_smmu_device_cfg_probe()1789 if (smmu->num_s2_context_banks > smmu->num_context_banks) { in arm_smmu_device_cfg_probe()1794 smmu->num_context_banks, smmu->num_s2_context_banks); in arm_smmu_device_cfg_probe()1795 smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks, in arm_smmu_device_cfg_probe()2127 if (smmu->num_context_banks > smmu->num_context_irqs) { in arm_smmu_device_probe()2130 smmu->num_context_irqs, smmu->num_context_banks); in arm_smmu_device_probe()2135 smmu->num_context_irqs = smmu->num_context_banks; in arm_smmu_device_probe()
192 count = smmu->num_context_banks; in qcom_adreno_smmu_alloc_context_bank()307 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; in qcom_smmu_cfg_probe()
239 for (idx = 0; idx < smmu->num_context_banks; idx++) { in nvidia_smmu_context_fault()
304 u32 num_context_banks; member