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Searched refs:nsapr (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/intc/
H A Darm_gic.c492 papr = &s->nsapr[regno][cpu]; in gic_activate_irq()
1552 return s->nsapr[regno + 2][cpu]; in gic_apr_ns_view()
1557 return s->nsapr[regno + 1][cpu]; in gic_apr_ns_view()
1562 return extract32(s->nsapr[0][cpu], 16, 16); in gic_apr_ns_view()
1567 return extract32(s->nsapr[0][cpu], 8, 8); in gic_apr_ns_view()
1583 s->nsapr[regno + 2][cpu] = value; in gic_apr_write_ns_view()
1588 s->nsapr[regno + 1][cpu] = value; in gic_apr_write_ns_view()
1593 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); in gic_apr_write_ns_view()
1598 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); in gic_apr_write_ns_view()
1675 *data = s->nsapr[regno][cpu]; in gic_cpu_read()
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H A Darm_gic_common.c122 VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
/openbmc/qemu/include/hw/intc/
H A Darm_gic_common.h118 uint32_t nsapr[GIC_NR_APRS][GIC_NCPU]; member