| /openbmc/qemu/hw/intc/ |
| H A D | rx_icu.c | 64 static void set_irq(RXICUState *icu, int n_IRQ, int req) in set_irq() argument
67 (icu->fir & R_FIR_FVCT_MASK) == n_IRQ) { in set_irq()
79 static void rxicu_request(RXICUState *icu, int n_IRQ) in rxicu_request() argument
83 enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7)); in rxicu_request()
84 if (n_IRQ > 0 && enable != 0 && qatomic_read(&icu->req_irq) < 0) { in rxicu_request()
85 qatomic_set(&icu->req_irq, n_IRQ); in rxicu_request()
86 set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ)); in rxicu_request()
90 static void rxicu_set_irq(void *opaque, int n_IRQ, int level) in rxicu_set_irq() argument
96 if (n_IRQ >= NR_IRQS) { in rxicu_set_irq()
97 error_report("%s: IRQ %d out of range", __func__, n_IRQ); in rxicu_set_irq()
[all …]
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| H A D | openpic.c | 195 static inline void IRQ_setbit(IRQQueue *q, int n_IRQ) in IRQ_setbit() argument
197 set_bit(n_IRQ, q->queue); in IRQ_setbit()
200 static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ) in IRQ_resetbit() argument
202 clear_bit(n_IRQ, q->queue); in IRQ_resetbit()
238 static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, in IRQ_local_pipe() argument
246 src = &opp->src[n_IRQ]; in IRQ_local_pipe()
249 __func__, n_IRQ, active, was_active); in IRQ_local_pipe()
253 __func__, src->output, n_IRQ, active, was_active, in IRQ_local_pipe()
264 __func__, src->output, n_CPU, n_IRQ); in IRQ_local_pipe()
270 __func__, src->output, n_CPU, n_IRQ); in IRQ_local_pipe()
[all …]
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| H A D | mips_gic.c | 58 static void gic_update_pin_for_irq(MIPSGICState *gic, int n_IRQ) in gic_update_pin_for_irq() argument
60 int vp = gic->irq_state[n_IRQ].map_vp; in gic_update_pin_for_irq()
61 int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK; in gic_update_pin_for_irq()
69 static void gic_set_irq(void *opaque, int n_IRQ, int level) in gic_set_irq() argument
73 gic->irq_state[n_IRQ].pending = (uint8_t) level; in gic_set_irq()
74 if (!gic->irq_state[n_IRQ].enabled) { in gic_set_irq()
78 gic_update_pin_for_irq(gic, n_IRQ); in gic_set_irq()
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| H A D | openpic_kvm.c | 54 static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level) in kvm_openpic_set_irq() argument
56 kvm_set_irq(kvm_state, n_IRQ, level); in kvm_openpic_set_irq()
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| /openbmc/linux/arch/powerpc/kvm/ |
| H A D | mpic.c | 128 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
281 static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ) in IRQ_setbit() argument
283 set_bit(n_IRQ, q->queue); in IRQ_setbit()
286 static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ) in IRQ_resetbit() argument
288 clear_bit(n_IRQ, q->queue); in IRQ_resetbit()
323 static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ, in IRQ_local_pipe() argument
331 src = &opp->src[n_IRQ]; in IRQ_local_pipe()
334 __func__, n_IRQ, active, was_active); in IRQ_local_pipe()
338 __func__, src->output, n_IRQ, active, was_active, in IRQ_local_pipe()
349 __func__, src->output, n_CPU, n_IRQ); in IRQ_local_pipe()
[all …]
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| /openbmc/qemu/include/hw/ppc/ |
| H A D | openpic.h | 101 int n_IRQ; member
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| H A D | ppc.h | 6 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
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