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Searched refs:n_IRQ (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/hw/intc/
H A Drx_icu.c83 enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7)); in rxicu_request()
86 set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ)); in rxicu_request()
96 if (n_IRQ >= NR_IRQS) { in rxicu_set_irq()
101 src = &icu->src[n_IRQ]; in rxicu_set_irq()
126 icu->ir[n_IRQ] = 0; in rxicu_set_irq()
135 icu->ir[n_IRQ] = 1; in rxicu_set_irq()
144 int n_IRQ; in rxicu_ack_irq() local
148 if (n_IRQ < 0) { in rxicu_ack_irq()
157 n_IRQ = -1; in rxicu_ack_irq()
161 n_IRQ = i; in rxicu_ack_irq()
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H A Dopenpic.c198 set_bit(n_IRQ, q->queue); in IRQ_setbit()
203 clear_bit(n_IRQ, q->queue); in IRQ_resetbit()
247 src = &opp->src[n_IRQ]; in IRQ_local_pipe()
332 src = &opp->src[n_IRQ]; in openpic_update_irq()
399 src = &opp->src[n_IRQ]; in openpic_set_irq()
516 opp->src[n_IRQ].ivpr = in write_IRQreg_ivpr()
526 opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); in write_IRQreg_ivpr()
687 uint32_t n_IRQ = tmr->n_IRQ; in qemu_timer_cb() local
696 opp->src[n_IRQ].destmask = read_IRQreg_idr(opp, n_IRQ); in qemu_timer_cb()
972 int s_IRQ, n_IRQ; in openpic_cpu_write_internal() local
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H A Dmips_gic.c58 static void gic_update_pin_for_irq(MIPSGICState *gic, int n_IRQ) in gic_update_pin_for_irq() argument
60 int vp = gic->irq_state[n_IRQ].map_vp; in gic_update_pin_for_irq()
61 int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK; in gic_update_pin_for_irq()
69 static void gic_set_irq(void *opaque, int n_IRQ, int level) in gic_set_irq() argument
73 gic->irq_state[n_IRQ].pending = (uint8_t) level; in gic_set_irq()
74 if (!gic->irq_state[n_IRQ].enabled) { in gic_set_irq()
78 gic_update_pin_for_irq(gic, n_IRQ); in gic_set_irq()
H A Dopenpic_kvm.c54 static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level) in kvm_openpic_set_irq() argument
56 kvm_set_irq(kvm_state, n_IRQ, level); in kvm_openpic_set_irq()
/openbmc/linux/arch/powerpc/kvm/
H A Dmpic.c283 set_bit(n_IRQ, q->queue); in IRQ_setbit()
331 src = &opp->src[n_IRQ]; in IRQ_local_pipe()
417 src = &opp->src[n_IRQ]; in openpic_update_irq()
480 if (n_IRQ >= MAX_IRQ) { in openpic_set_irq()
485 src = &opp->src[n_IRQ]; in openpic_set_irq()
650 opp->src[n_IRQ].ivpr = in write_IRQreg_ivpr()
659 opp->src[n_IRQ].level = in write_IRQreg_ivpr()
674 opp->src[n_IRQ].ivpr); in write_IRQreg_ivpr()
1029 int s_IRQ, n_IRQ; in openpic_cpu_write_internal() local
1097 if (n_IRQ != -1 && in openpic_cpu_write_internal()
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/openbmc/qemu/include/hw/ppc/
H A Dopenpic.h101 int n_IRQ; member
H A Dppc.h6 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);