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Searched refs:mvip (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_helper.c544 uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; in riscv_cpu_sirq_pending()
608 irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; in riscv_cpu_local_irq_pending()
830 irqf = env->mvien & env->mvip & env->sie; in riscv_cpu_interrupt()
2266 bool s_injected = env->mvip & (1ULL << cause) & env->mvien && in riscv_cpu_do_interrupt()
H A Dmachine.c433 VMSTATE_UINT64(env.mvip, RISCVCPU),
H A Dcpu.h334 uint64_t mvip; member
H A Dcsr.c3771 old_mvip = env->mvip; in rmw_mvip64()
3778 env->mvip = (env->mvip & ~wr_mask_mvip) | (new_val & wr_mask_mvip); in rmw_mvip64()