Searched refs:mvien (Results 1 – 4 of 4) sorted by relevance
406 uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; in riscv_cpu_sirq_pending()458 irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; in riscv_cpu_local_irq_pending()665 irqf = env->mvien & env->mvip & env->sie; in riscv_cpu_interrupt()1647 bool s_injected = env->mvip & (1 << cause) & env->mvien && in riscv_cpu_do_interrupt()
1596 *ret_val = env->mvien; in rmw_mvien64()1599 env->mvien = (env->mvien & ~mask) | (new_val & mask); in rmw_mvien64()1776 if (env->priv == PRV_S && env->mvien & MIP_SEIP && in rmw_xireg()1847 if (env->mvien & MIP_SEIP && env->priv == PRV_S) { in rmw_xtopei()2479 (env->mideleg | ~env->mvien)) | MIP_STIP; in rmw_mvip64()2481 (~env->mideleg & env->mvien); in rmw_mvip64()2496 alias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()2497 nalias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()2693 (~env->mideleg & env->mvien); in rmw_sie64()2935 uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask; in rmw_sip64()[all …]
385 VMSTATE_UINT64(env.mvien, RISCVCPU),
247 uint64_t mvien; member