Searched refs:mstr (Results 1 – 14 of 14) sorted by relevance
90 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001; in cl_som_imx7_spl_dram_cfg_size()101 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; in cl_som_imx7_spl_dram_cfg_size()112 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; in cl_som_imx7_spl_dram_cfg_size()123 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; in cl_som_imx7_spl_dram_cfg_size()
44 writel(ddrc_regs_val->mstr, &ddrc_regs->mstr); in mx7_dram_cfg()118 reg_val = readl(&ddrc_regs->mstr); in imx_ddr_size()
211 writel(0x01040001, &mctl_ctl->mstr); in mctl_init()213 writel(0x01040401, &mctl_ctl->mstr); in mctl_init()249 setbits_le32(&mctl_ctl->mstr, 0x1000); in mctl_init()
596 &mctl_ctl->mstr); in mctl_channel_init()
450 0x80000000, &mctl_ctl->mstr); in mctl_com_init()
25 .mstr = 0x01040001,
15 u32 mstr; /* 0x0000 */ member
41 u32 mstr; member
46 DDRCTL_REG_REG(mstr),451 if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) in stm32mp1_ddr_init()
11 u32 mstr ; /* 0x0 Master*/ member
66 u32 mstr; /* 0x000 */ member
41 u32 mstr; /* 0x00 master register */ member
92 u32 mstr; /* 0x00 */ member
69 u32 mstr; member