1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Texas Instruments Keystone SoCs
4 *
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
6 * https://www.ti.com
7 *
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/msi.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/resource.h>
28 #include <linux/signal.h>
29
30 #include "../../pci.h"
31 #include "pcie-designware.h"
32
33 #define PCIE_VENDORID_MASK 0xffff
34 #define PCIE_DEVICEID_SHIFT 16
35
36 /* Application registers */
37 #define CMD_STATUS 0x004
38 #define LTSSM_EN_VAL BIT(0)
39 #define OB_XLAT_EN_VAL BIT(1)
40 #define DBI_CS2 BIT(5)
41
42 #define CFG_SETUP 0x008
43 #define CFG_BUS(x) (((x) & 0xff) << 16)
44 #define CFG_DEVICE(x) (((x) & 0x1f) << 8)
45 #define CFG_FUNC(x) ((x) & 0x7)
46 #define CFG_TYPE1 BIT(24)
47
48 #define OB_SIZE 0x030
49 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
50 #define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
51 #define OB_ENABLEN BIT(0)
52 #define OB_WIN_SIZE 8 /* 8MB */
53
54 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
55 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
56 #define PCIE_EP_IRQ_SET 0x64
57 #define PCIE_EP_IRQ_CLR 0x68
58 #define INT_ENABLE BIT(0)
59
60 /* IRQ register defines */
61 #define IRQ_EOI 0x050
62
63 #define MSI_IRQ 0x054
64 #define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4))
65 #define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4))
66 #define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4))
67 #define MSI_IRQ_OFFSET 4
68
69 #define IRQ_STATUS(n) (0x184 + ((n) << 4))
70 #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4))
71 #define INTx_EN BIT(0)
72
73 #define ERR_IRQ_STATUS 0x1c4
74 #define ERR_IRQ_ENABLE_SET 0x1c8
75 #define ERR_AER BIT(5) /* ECRC error */
76 #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */
77 #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
78 #define ERR_CORR BIT(3) /* Correctable error */
79 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
80 #define ERR_FATAL BIT(1) /* Fatal error */
81 #define ERR_SYS BIT(0) /* System error */
82 #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
83 ERR_NONFATAL | ERR_FATAL | ERR_SYS)
84
85 /* PCIE controller device IDs */
86 #define PCIE_RC_K2HK 0xb008
87 #define PCIE_RC_K2E 0xb009
88 #define PCIE_RC_K2L 0xb00a
89 #define PCIE_RC_K2G 0xb00b
90
91 #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1)
92 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1)
93
94 #define EP 0x0
95 #define LEG_EP 0x1
96 #define RC 0x2
97
98 #define KS_PCIE_SYSCLOCKOUTEN BIT(0)
99
100 #define AM654_PCIE_DEV_TYPE_MASK 0x3
101 #define AM654_WIN_SIZE SZ_64K
102
103 #define APP_ADDR_SPACE_0 (16 * SZ_1K)
104
105 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
106
107 struct ks_pcie_of_data {
108 enum dw_pcie_device_mode mode;
109 const struct dw_pcie_host_ops *host_ops;
110 const struct dw_pcie_ep_ops *ep_ops;
111 u32 version;
112 };
113
114 struct keystone_pcie {
115 struct dw_pcie *pci;
116 /* PCI Device ID */
117 u32 device_id;
118 int legacy_host_irqs[PCI_NUM_INTX];
119 struct device_node *legacy_intc_np;
120
121 int msi_host_irq;
122 int num_lanes;
123 u32 num_viewport;
124 struct phy **phy;
125 struct device_link **link;
126 struct device_node *msi_intc_np;
127 struct irq_domain *legacy_irq_domain;
128 struct device_node *np;
129
130 /* Application register space */
131 void __iomem *va_app_base; /* DT 1st resource */
132 struct resource app;
133 bool is_am6;
134 };
135
ks_pcie_app_readl(struct keystone_pcie * ks_pcie,u32 offset)136 static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
137 {
138 return readl(ks_pcie->va_app_base + offset);
139 }
140
ks_pcie_app_writel(struct keystone_pcie * ks_pcie,u32 offset,u32 val)141 static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
142 u32 val)
143 {
144 writel(val, ks_pcie->va_app_base + offset);
145 }
146
ks_pcie_msi_irq_ack(struct irq_data * data)147 static void ks_pcie_msi_irq_ack(struct irq_data *data)
148 {
149 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
150 struct keystone_pcie *ks_pcie;
151 u32 irq = data->hwirq;
152 struct dw_pcie *pci;
153 u32 reg_offset;
154 u32 bit_pos;
155
156 pci = to_dw_pcie_from_pp(pp);
157 ks_pcie = to_keystone_pcie(pci);
158
159 reg_offset = irq % 8;
160 bit_pos = irq >> 3;
161
162 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset),
163 BIT(bit_pos));
164 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
165 }
166
ks_pcie_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)167 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
168 {
169 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
170 struct keystone_pcie *ks_pcie;
171 struct dw_pcie *pci;
172 u64 msi_target;
173
174 pci = to_dw_pcie_from_pp(pp);
175 ks_pcie = to_keystone_pcie(pci);
176
177 msi_target = ks_pcie->app.start + MSI_IRQ;
178 msg->address_lo = lower_32_bits(msi_target);
179 msg->address_hi = upper_32_bits(msi_target);
180 msg->data = data->hwirq;
181
182 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
183 (int)data->hwirq, msg->address_hi, msg->address_lo);
184 }
185
ks_pcie_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)186 static int ks_pcie_msi_set_affinity(struct irq_data *irq_data,
187 const struct cpumask *mask, bool force)
188 {
189 return -EINVAL;
190 }
191
ks_pcie_msi_mask(struct irq_data * data)192 static void ks_pcie_msi_mask(struct irq_data *data)
193 {
194 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
195 struct keystone_pcie *ks_pcie;
196 u32 irq = data->hwirq;
197 struct dw_pcie *pci;
198 unsigned long flags;
199 u32 reg_offset;
200 u32 bit_pos;
201
202 raw_spin_lock_irqsave(&pp->lock, flags);
203
204 pci = to_dw_pcie_from_pp(pp);
205 ks_pcie = to_keystone_pcie(pci);
206
207 reg_offset = irq % 8;
208 bit_pos = irq >> 3;
209
210 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset),
211 BIT(bit_pos));
212
213 raw_spin_unlock_irqrestore(&pp->lock, flags);
214 }
215
ks_pcie_msi_unmask(struct irq_data * data)216 static void ks_pcie_msi_unmask(struct irq_data *data)
217 {
218 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
219 struct keystone_pcie *ks_pcie;
220 u32 irq = data->hwirq;
221 struct dw_pcie *pci;
222 unsigned long flags;
223 u32 reg_offset;
224 u32 bit_pos;
225
226 raw_spin_lock_irqsave(&pp->lock, flags);
227
228 pci = to_dw_pcie_from_pp(pp);
229 ks_pcie = to_keystone_pcie(pci);
230
231 reg_offset = irq % 8;
232 bit_pos = irq >> 3;
233
234 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset),
235 BIT(bit_pos));
236
237 raw_spin_unlock_irqrestore(&pp->lock, flags);
238 }
239
240 static struct irq_chip ks_pcie_msi_irq_chip = {
241 .name = "KEYSTONE-PCI-MSI",
242 .irq_ack = ks_pcie_msi_irq_ack,
243 .irq_compose_msi_msg = ks_pcie_compose_msi_msg,
244 .irq_set_affinity = ks_pcie_msi_set_affinity,
245 .irq_mask = ks_pcie_msi_mask,
246 .irq_unmask = ks_pcie_msi_unmask,
247 };
248
249 /**
250 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
251 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
252 * PCIe host controller driver information.
253 *
254 * Since modification of dbi_cs2 involves different clock domain, read the
255 * status back to ensure the transition is complete.
256 */
ks_pcie_set_dbi_mode(struct keystone_pcie * ks_pcie)257 static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
258 {
259 u32 val;
260
261 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
262 val |= DBI_CS2;
263 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
264
265 do {
266 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
267 } while (!(val & DBI_CS2));
268 }
269
270 /**
271 * ks_pcie_clear_dbi_mode() - Disable DBI mode
272 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
273 * PCIe host controller driver information.
274 *
275 * Since modification of dbi_cs2 involves different clock domain, read the
276 * status back to ensure the transition is complete.
277 */
ks_pcie_clear_dbi_mode(struct keystone_pcie * ks_pcie)278 static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
279 {
280 u32 val;
281
282 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
283 val &= ~DBI_CS2;
284 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
285
286 do {
287 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
288 } while (val & DBI_CS2);
289 }
290
ks_pcie_msi_host_init(struct dw_pcie_rp * pp)291 static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
292 {
293 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
294 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
295
296 /* Configure and set up BAR0 */
297 ks_pcie_set_dbi_mode(ks_pcie);
298
299 /* Enable BAR0 */
300 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
301 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
302
303 ks_pcie_clear_dbi_mode(ks_pcie);
304
305 /*
306 * For BAR0, just setting bus address for inbound writes (MSI) should
307 * be sufficient. Use physical address to avoid any conflicts.
308 */
309 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
310
311 pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
312 return dw_pcie_allocate_domains(pp);
313 }
314
ks_pcie_handle_legacy_irq(struct keystone_pcie * ks_pcie,int offset)315 static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
316 int offset)
317 {
318 struct dw_pcie *pci = ks_pcie->pci;
319 struct device *dev = pci->dev;
320 u32 pending;
321
322 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset));
323
324 if (BIT(0) & pending) {
325 dev_dbg(dev, ": irq: irq_offset %d", offset);
326 generic_handle_domain_irq(ks_pcie->legacy_irq_domain, offset);
327 }
328
329 /* EOI the INTx interrupt */
330 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
331 }
332
ks_pcie_enable_error_irq(struct keystone_pcie * ks_pcie)333 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
334 {
335 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
336 }
337
ks_pcie_handle_error_irq(struct keystone_pcie * ks_pcie)338 static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
339 {
340 u32 reg;
341 struct device *dev = ks_pcie->pci->dev;
342
343 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS);
344 if (!reg)
345 return IRQ_NONE;
346
347 if (reg & ERR_SYS)
348 dev_err(dev, "System Error\n");
349
350 if (reg & ERR_FATAL)
351 dev_err(dev, "Fatal Error\n");
352
353 if (reg & ERR_NONFATAL)
354 dev_dbg(dev, "Non Fatal Error\n");
355
356 if (reg & ERR_CORR)
357 dev_dbg(dev, "Correctable Error\n");
358
359 if (!ks_pcie->is_am6 && (reg & ERR_AXI))
360 dev_err(dev, "AXI tag lookup fatal Error\n");
361
362 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER)))
363 dev_err(dev, "ECRC Error\n");
364
365 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg);
366
367 return IRQ_HANDLED;
368 }
369
ks_pcie_ack_legacy_irq(struct irq_data * d)370 static void ks_pcie_ack_legacy_irq(struct irq_data *d)
371 {
372 }
373
ks_pcie_mask_legacy_irq(struct irq_data * d)374 static void ks_pcie_mask_legacy_irq(struct irq_data *d)
375 {
376 }
377
ks_pcie_unmask_legacy_irq(struct irq_data * d)378 static void ks_pcie_unmask_legacy_irq(struct irq_data *d)
379 {
380 }
381
382 static struct irq_chip ks_pcie_legacy_irq_chip = {
383 .name = "Keystone-PCI-Legacy-IRQ",
384 .irq_ack = ks_pcie_ack_legacy_irq,
385 .irq_mask = ks_pcie_mask_legacy_irq,
386 .irq_unmask = ks_pcie_unmask_legacy_irq,
387 };
388
ks_pcie_init_legacy_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw_irq)389 static int ks_pcie_init_legacy_irq_map(struct irq_domain *d,
390 unsigned int irq,
391 irq_hw_number_t hw_irq)
392 {
393 irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip,
394 handle_level_irq);
395 irq_set_chip_data(irq, d->host_data);
396
397 return 0;
398 }
399
400 static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = {
401 .map = ks_pcie_init_legacy_irq_map,
402 .xlate = irq_domain_xlate_onetwocell,
403 };
404
ks_pcie_setup_rc_app_regs(struct keystone_pcie * ks_pcie)405 static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
406 {
407 u32 val;
408 u32 num_viewport = ks_pcie->num_viewport;
409 struct dw_pcie *pci = ks_pcie->pci;
410 struct dw_pcie_rp *pp = &pci->pp;
411 struct resource_entry *entry;
412 struct resource *mem;
413 u64 start, end;
414 int i;
415
416 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
417 if (!entry)
418 return -ENODEV;
419
420 mem = entry->res;
421 start = mem->start;
422 end = mem->end;
423
424 /* Disable BARs for inbound access */
425 ks_pcie_set_dbi_mode(ks_pcie);
426 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
427 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
428 ks_pcie_clear_dbi_mode(ks_pcie);
429
430 if (ks_pcie->is_am6)
431 return 0;
432
433 val = ilog2(OB_WIN_SIZE);
434 ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
435
436 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
437 for (i = 0; i < num_viewport && (start < end); i++) {
438 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i),
439 lower_32_bits(start) | OB_ENABLEN);
440 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i),
441 upper_32_bits(start));
442 start += OB_WIN_SIZE * SZ_1M;
443 }
444
445 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
446 val |= OB_XLAT_EN_VAL;
447 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
448
449 return 0;
450 }
451
ks_pcie_other_map_bus(struct pci_bus * bus,unsigned int devfn,int where)452 static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
453 unsigned int devfn, int where)
454 {
455 struct dw_pcie_rp *pp = bus->sysdata;
456 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
457 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
458 u32 reg;
459
460 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
461 CFG_FUNC(PCI_FUNC(devfn));
462 if (!pci_is_root_bus(bus->parent))
463 reg |= CFG_TYPE1;
464 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
465
466 return pp->va_cfg0_base + where;
467 }
468
469 static struct pci_ops ks_child_pcie_ops = {
470 .map_bus = ks_pcie_other_map_bus,
471 .read = pci_generic_config_read,
472 .write = pci_generic_config_write,
473 };
474
475 static struct pci_ops ks_pcie_ops = {
476 .map_bus = dw_pcie_own_conf_map_bus,
477 .read = pci_generic_config_read,
478 .write = pci_generic_config_write,
479 };
480
481 /**
482 * ks_pcie_link_up() - Check if link up
483 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host
484 * controller driver information.
485 */
ks_pcie_link_up(struct dw_pcie * pci)486 static int ks_pcie_link_up(struct dw_pcie *pci)
487 {
488 u32 val;
489
490 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
491 val &= PORT_LOGIC_LTSSM_STATE_MASK;
492 return (val == PORT_LOGIC_LTSSM_STATE_L0);
493 }
494
ks_pcie_stop_link(struct dw_pcie * pci)495 static void ks_pcie_stop_link(struct dw_pcie *pci)
496 {
497 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
498 u32 val;
499
500 /* Disable Link training */
501 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
502 val &= ~LTSSM_EN_VAL;
503 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
504 }
505
ks_pcie_start_link(struct dw_pcie * pci)506 static int ks_pcie_start_link(struct dw_pcie *pci)
507 {
508 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
509 u32 val;
510
511 /* Initiate Link Training */
512 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
513 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
514
515 return 0;
516 }
517
ks_pcie_quirk(struct pci_dev * dev)518 static void ks_pcie_quirk(struct pci_dev *dev)
519 {
520 struct pci_bus *bus = dev->bus;
521 struct pci_dev *bridge;
522 static const struct pci_device_id rc_pci_devids[] = {
523 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
524 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
525 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
526 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
527 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
528 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
529 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
530 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
531 { 0, },
532 };
533
534 if (pci_is_root_bus(bus))
535 bridge = dev;
536
537 /* look for the host bridge */
538 while (!pci_is_root_bus(bus)) {
539 bridge = bus->self;
540 bus = bus->parent;
541 }
542
543 if (!bridge)
544 return;
545
546 /*
547 * Keystone PCI controller has a h/w limitation of
548 * 256 bytes maximum read request size. It can't handle
549 * anything higher than this. So force this limit on
550 * all downstream devices.
551 */
552 if (pci_match_id(rc_pci_devids, bridge)) {
553 if (pcie_get_readrq(dev) > 256) {
554 dev_info(&dev->dev, "limiting MRRS to 256\n");
555 pcie_set_readrq(dev, 256);
556 }
557 }
558 }
559 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
560
ks_pcie_msi_irq_handler(struct irq_desc * desc)561 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
562 {
563 unsigned int irq = desc->irq_data.hwirq;
564 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
565 u32 offset = irq - ks_pcie->msi_host_irq;
566 struct dw_pcie *pci = ks_pcie->pci;
567 struct dw_pcie_rp *pp = &pci->pp;
568 struct device *dev = pci->dev;
569 struct irq_chip *chip = irq_desc_get_chip(desc);
570 u32 vector, reg, pos;
571
572 dev_dbg(dev, "%s, irq %d\n", __func__, irq);
573
574 /*
575 * The chained irq handler installation would have replaced normal
576 * interrupt driver handler so we need to take care of mask/unmask and
577 * ack operation.
578 */
579 chained_irq_enter(chip, desc);
580
581 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset));
582 /*
583 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
584 * shows 1, 9, 17, 25 and so forth
585 */
586 for (pos = 0; pos < 4; pos++) {
587 if (!(reg & BIT(pos)))
588 continue;
589
590 vector = offset + (pos << 3);
591 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector);
592 generic_handle_domain_irq(pp->irq_domain, vector);
593 }
594
595 chained_irq_exit(chip, desc);
596 }
597
598 /**
599 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
600 * @desc: Pointer to irq descriptor
601 *
602 * Traverse through pending legacy interrupts and invoke handler for each. Also
603 * takes care of interrupt controller level mask/ack operation.
604 */
ks_pcie_legacy_irq_handler(struct irq_desc * desc)605 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
606 {
607 unsigned int irq = irq_desc_get_irq(desc);
608 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
609 struct dw_pcie *pci = ks_pcie->pci;
610 struct device *dev = pci->dev;
611 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
612 struct irq_chip *chip = irq_desc_get_chip(desc);
613
614 dev_dbg(dev, ": Handling legacy irq %d\n", irq);
615
616 /*
617 * The chained irq handler installation would have replaced normal
618 * interrupt driver handler so we need to take care of mask/unmask and
619 * ack operation.
620 */
621 chained_irq_enter(chip, desc);
622 ks_pcie_handle_legacy_irq(ks_pcie, irq_offset);
623 chained_irq_exit(chip, desc);
624 }
625
ks_pcie_config_msi_irq(struct keystone_pcie * ks_pcie)626 static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie)
627 {
628 struct device *dev = ks_pcie->pci->dev;
629 struct device_node *np = ks_pcie->np;
630 struct device_node *intc_np;
631 struct irq_data *irq_data;
632 int irq_count, irq, ret, i;
633
634 if (!IS_ENABLED(CONFIG_PCI_MSI))
635 return 0;
636
637 intc_np = of_get_child_by_name(np, "msi-interrupt-controller");
638 if (!intc_np) {
639 if (ks_pcie->is_am6)
640 return 0;
641 dev_warn(dev, "msi-interrupt-controller node is absent\n");
642 return -EINVAL;
643 }
644
645 irq_count = of_irq_count(intc_np);
646 if (!irq_count) {
647 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n");
648 ret = -EINVAL;
649 goto err;
650 }
651
652 for (i = 0; i < irq_count; i++) {
653 irq = irq_of_parse_and_map(intc_np, i);
654 if (!irq) {
655 ret = -EINVAL;
656 goto err;
657 }
658
659 if (!ks_pcie->msi_host_irq) {
660 irq_data = irq_get_irq_data(irq);
661 if (!irq_data) {
662 ret = -EINVAL;
663 goto err;
664 }
665 ks_pcie->msi_host_irq = irq_data->hwirq;
666 }
667
668 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler,
669 ks_pcie);
670 }
671
672 of_node_put(intc_np);
673 return 0;
674
675 err:
676 of_node_put(intc_np);
677 return ret;
678 }
679
ks_pcie_config_legacy_irq(struct keystone_pcie * ks_pcie)680 static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie)
681 {
682 struct device *dev = ks_pcie->pci->dev;
683 struct irq_domain *legacy_irq_domain;
684 struct device_node *np = ks_pcie->np;
685 struct device_node *intc_np;
686 int irq_count, irq, ret = 0, i;
687
688 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller");
689 if (!intc_np) {
690 /*
691 * Since legacy interrupts are modeled as edge-interrupts in
692 * AM6, keep it disabled for now.
693 */
694 if (ks_pcie->is_am6)
695 return 0;
696 dev_warn(dev, "legacy-interrupt-controller node is absent\n");
697 return -EINVAL;
698 }
699
700 irq_count = of_irq_count(intc_np);
701 if (!irq_count) {
702 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n");
703 ret = -EINVAL;
704 goto err;
705 }
706
707 for (i = 0; i < irq_count; i++) {
708 irq = irq_of_parse_and_map(intc_np, i);
709 if (!irq) {
710 ret = -EINVAL;
711 goto err;
712 }
713 ks_pcie->legacy_host_irqs[i] = irq;
714
715 irq_set_chained_handler_and_data(irq,
716 ks_pcie_legacy_irq_handler,
717 ks_pcie);
718 }
719
720 legacy_irq_domain =
721 irq_domain_add_linear(intc_np, PCI_NUM_INTX,
722 &ks_pcie_legacy_irq_domain_ops, NULL);
723 if (!legacy_irq_domain) {
724 dev_err(dev, "Failed to add irq domain for legacy irqs\n");
725 ret = -EINVAL;
726 goto err;
727 }
728 ks_pcie->legacy_irq_domain = legacy_irq_domain;
729
730 for (i = 0; i < PCI_NUM_INTX; i++)
731 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN);
732
733 err:
734 of_node_put(intc_np);
735 return ret;
736 }
737
738 #ifdef CONFIG_ARM
739 /*
740 * When a PCI device does not exist during config cycles, keystone host
741 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE).
742 * This handler always returns 0 for this kind of fault.
743 */
ks_pcie_fault(unsigned long addr,unsigned int fsr,struct pt_regs * regs)744 static int ks_pcie_fault(unsigned long addr, unsigned int fsr,
745 struct pt_regs *regs)
746 {
747 unsigned long instr = *(unsigned long *) instruction_pointer(regs);
748
749 if ((instr & 0x0e100090) == 0x00100090) {
750 int reg = (instr >> 12) & 15;
751
752 regs->uregs[reg] = -1;
753 regs->ARM_pc += 4;
754 }
755
756 return 0;
757 }
758 #endif
759
ks_pcie_init_id(struct keystone_pcie * ks_pcie)760 static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
761 {
762 int ret;
763 unsigned int id;
764 struct regmap *devctrl_regs;
765 struct dw_pcie *pci = ks_pcie->pci;
766 struct device *dev = pci->dev;
767 struct device_node *np = dev->of_node;
768 struct of_phandle_args args;
769 unsigned int offset = 0;
770
771 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id");
772 if (IS_ERR(devctrl_regs))
773 return PTR_ERR(devctrl_regs);
774
775 /* Do not error out to maintain old DT compatibility */
776 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args);
777 if (!ret)
778 offset = args.args[0];
779
780 ret = regmap_read(devctrl_regs, offset, &id);
781 if (ret)
782 return ret;
783
784 dw_pcie_dbi_ro_wr_en(pci);
785 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK);
786 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT);
787 dw_pcie_dbi_ro_wr_dis(pci);
788
789 return 0;
790 }
791
ks_pcie_host_init(struct dw_pcie_rp * pp)792 static int __init ks_pcie_host_init(struct dw_pcie_rp *pp)
793 {
794 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
795 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
796 int ret;
797
798 pp->bridge->ops = &ks_pcie_ops;
799 if (!ks_pcie->is_am6)
800 pp->bridge->child_ops = &ks_child_pcie_ops;
801
802 ret = ks_pcie_config_legacy_irq(ks_pcie);
803 if (ret)
804 return ret;
805
806 ret = ks_pcie_config_msi_irq(ks_pcie);
807 if (ret)
808 return ret;
809
810 ks_pcie_stop_link(pci);
811 ret = ks_pcie_setup_rc_app_regs(ks_pcie);
812 if (ret)
813 return ret;
814
815 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
816 pci->dbi_base + PCI_IO_BASE);
817
818 ret = ks_pcie_init_id(ks_pcie);
819 if (ret < 0)
820 return ret;
821
822 #ifdef CONFIG_ARM
823 /*
824 * PCIe access errors that result into OCP errors are caught by ARM as
825 * "External aborts"
826 */
827 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0,
828 "Asynchronous external abort");
829 #endif
830
831 return 0;
832 }
833
834 static const struct dw_pcie_host_ops ks_pcie_host_ops = {
835 .host_init = ks_pcie_host_init,
836 .msi_host_init = ks_pcie_msi_host_init,
837 };
838
839 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = {
840 .host_init = ks_pcie_host_init,
841 };
842
ks_pcie_err_irq_handler(int irq,void * priv)843 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv)
844 {
845 struct keystone_pcie *ks_pcie = priv;
846
847 return ks_pcie_handle_error_irq(ks_pcie);
848 }
849
ks_pcie_am654_write_dbi2(struct dw_pcie * pci,void __iomem * base,u32 reg,size_t size,u32 val)850 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base,
851 u32 reg, size_t size, u32 val)
852 {
853 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
854
855 ks_pcie_set_dbi_mode(ks_pcie);
856 dw_pcie_write(base + reg, size, val);
857 ks_pcie_clear_dbi_mode(ks_pcie);
858 }
859
860 static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = {
861 .start_link = ks_pcie_start_link,
862 .stop_link = ks_pcie_stop_link,
863 .link_up = ks_pcie_link_up,
864 .write_dbi2 = ks_pcie_am654_write_dbi2,
865 };
866
ks_pcie_am654_ep_init(struct dw_pcie_ep * ep)867 static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep)
868 {
869 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
870 int flags;
871
872 ep->page_size = AM654_WIN_SIZE;
873 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
874 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1);
875 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags);
876 }
877
ks_pcie_am654_raise_legacy_irq(struct keystone_pcie * ks_pcie)878 static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie)
879 {
880 struct dw_pcie *pci = ks_pcie->pci;
881 u8 int_pin;
882
883 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN);
884 if (int_pin == 0 || int_pin > 4)
885 return;
886
887 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin),
888 INT_ENABLE);
889 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE);
890 mdelay(1);
891 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE);
892 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin),
893 INT_ENABLE);
894 }
895
ks_pcie_am654_raise_irq(struct dw_pcie_ep * ep,u8 func_no,enum pci_epc_irq_type type,u16 interrupt_num)896 static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
897 enum pci_epc_irq_type type,
898 u16 interrupt_num)
899 {
900 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
901 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
902
903 switch (type) {
904 case PCI_EPC_IRQ_LEGACY:
905 ks_pcie_am654_raise_legacy_irq(ks_pcie);
906 break;
907 case PCI_EPC_IRQ_MSI:
908 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
909 break;
910 case PCI_EPC_IRQ_MSIX:
911 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
912 break;
913 default:
914 dev_err(pci->dev, "UNKNOWN IRQ type\n");
915 return -EINVAL;
916 }
917
918 return 0;
919 }
920
921 static const struct pci_epc_features ks_pcie_am654_epc_features = {
922 .linkup_notifier = false,
923 .msi_capable = true,
924 .msix_capable = true,
925 .reserved_bar = 1 << BAR_0 | 1 << BAR_1,
926 .bar_fixed_64bit = 1 << BAR_0,
927 .bar_fixed_size[2] = SZ_1M,
928 .bar_fixed_size[3] = SZ_64K,
929 .bar_fixed_size[4] = 256,
930 .bar_fixed_size[5] = SZ_1M,
931 .align = SZ_1M,
932 };
933
934 static const struct pci_epc_features*
ks_pcie_am654_get_features(struct dw_pcie_ep * ep)935 ks_pcie_am654_get_features(struct dw_pcie_ep *ep)
936 {
937 return &ks_pcie_am654_epc_features;
938 }
939
940 static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = {
941 .ep_init = ks_pcie_am654_ep_init,
942 .raise_irq = ks_pcie_am654_raise_irq,
943 .get_features = &ks_pcie_am654_get_features,
944 };
945
ks_pcie_disable_phy(struct keystone_pcie * ks_pcie)946 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie)
947 {
948 int num_lanes = ks_pcie->num_lanes;
949
950 while (num_lanes--) {
951 phy_power_off(ks_pcie->phy[num_lanes]);
952 phy_exit(ks_pcie->phy[num_lanes]);
953 }
954 }
955
ks_pcie_enable_phy(struct keystone_pcie * ks_pcie)956 static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie)
957 {
958 int i;
959 int ret;
960 int num_lanes = ks_pcie->num_lanes;
961
962 for (i = 0; i < num_lanes; i++) {
963 ret = phy_reset(ks_pcie->phy[i]);
964 if (ret < 0)
965 goto err_phy;
966
967 ret = phy_init(ks_pcie->phy[i]);
968 if (ret < 0)
969 goto err_phy;
970
971 ret = phy_power_on(ks_pcie->phy[i]);
972 if (ret < 0) {
973 phy_exit(ks_pcie->phy[i]);
974 goto err_phy;
975 }
976 }
977
978 return 0;
979
980 err_phy:
981 while (--i >= 0) {
982 phy_power_off(ks_pcie->phy[i]);
983 phy_exit(ks_pcie->phy[i]);
984 }
985
986 return ret;
987 }
988
ks_pcie_set_mode(struct device * dev)989 static int ks_pcie_set_mode(struct device *dev)
990 {
991 struct device_node *np = dev->of_node;
992 struct of_phandle_args args;
993 unsigned int offset = 0;
994 struct regmap *syscon;
995 u32 val;
996 u32 mask;
997 int ret = 0;
998
999 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode");
1000 if (IS_ERR(syscon))
1001 return 0;
1002
1003 /* Do not error out to maintain old DT compatibility */
1004 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args);
1005 if (!ret)
1006 offset = args.args[0];
1007
1008 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN;
1009 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN;
1010
1011 ret = regmap_update_bits(syscon, offset, mask, val);
1012 if (ret) {
1013 dev_err(dev, "failed to set pcie mode\n");
1014 return ret;
1015 }
1016
1017 return 0;
1018 }
1019
ks_pcie_am654_set_mode(struct device * dev,enum dw_pcie_device_mode mode)1020 static int ks_pcie_am654_set_mode(struct device *dev,
1021 enum dw_pcie_device_mode mode)
1022 {
1023 struct device_node *np = dev->of_node;
1024 struct of_phandle_args args;
1025 unsigned int offset = 0;
1026 struct regmap *syscon;
1027 u32 val;
1028 u32 mask;
1029 int ret = 0;
1030
1031 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode");
1032 if (IS_ERR(syscon))
1033 return 0;
1034
1035 /* Do not error out to maintain old DT compatibility */
1036 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args);
1037 if (!ret)
1038 offset = args.args[0];
1039
1040 mask = AM654_PCIE_DEV_TYPE_MASK;
1041
1042 switch (mode) {
1043 case DW_PCIE_RC_TYPE:
1044 val = RC;
1045 break;
1046 case DW_PCIE_EP_TYPE:
1047 val = EP;
1048 break;
1049 default:
1050 dev_err(dev, "INVALID device type %d\n", mode);
1051 return -EINVAL;
1052 }
1053
1054 ret = regmap_update_bits(syscon, offset, mask, val);
1055 if (ret) {
1056 dev_err(dev, "failed to set pcie mode\n");
1057 return ret;
1058 }
1059
1060 return 0;
1061 }
1062
1063 static const struct ks_pcie_of_data ks_pcie_rc_of_data = {
1064 .host_ops = &ks_pcie_host_ops,
1065 .version = DW_PCIE_VER_365A,
1066 };
1067
1068 static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = {
1069 .host_ops = &ks_pcie_am654_host_ops,
1070 .mode = DW_PCIE_RC_TYPE,
1071 .version = DW_PCIE_VER_490A,
1072 };
1073
1074 static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = {
1075 .ep_ops = &ks_pcie_am654_ep_ops,
1076 .mode = DW_PCIE_EP_TYPE,
1077 .version = DW_PCIE_VER_490A,
1078 };
1079
1080 static const struct of_device_id ks_pcie_of_match[] = {
1081 {
1082 .type = "pci",
1083 .data = &ks_pcie_rc_of_data,
1084 .compatible = "ti,keystone-pcie",
1085 },
1086 {
1087 .data = &ks_pcie_am654_rc_of_data,
1088 .compatible = "ti,am654-pcie-rc",
1089 },
1090 {
1091 .data = &ks_pcie_am654_ep_of_data,
1092 .compatible = "ti,am654-pcie-ep",
1093 },
1094 { },
1095 };
1096
ks_pcie_probe(struct platform_device * pdev)1097 static int ks_pcie_probe(struct platform_device *pdev)
1098 {
1099 const struct dw_pcie_host_ops *host_ops;
1100 const struct dw_pcie_ep_ops *ep_ops;
1101 struct device *dev = &pdev->dev;
1102 struct device_node *np = dev->of_node;
1103 const struct ks_pcie_of_data *data;
1104 enum dw_pcie_device_mode mode;
1105 struct dw_pcie *pci;
1106 struct keystone_pcie *ks_pcie;
1107 struct device_link **link;
1108 struct gpio_desc *gpiod;
1109 struct resource *res;
1110 void __iomem *base;
1111 u32 num_viewport;
1112 struct phy **phy;
1113 u32 num_lanes;
1114 char name[10];
1115 u32 version;
1116 int ret;
1117 int irq;
1118 int i;
1119
1120 data = of_device_get_match_data(dev);
1121 if (!data)
1122 return -EINVAL;
1123
1124 version = data->version;
1125 host_ops = data->host_ops;
1126 ep_ops = data->ep_ops;
1127 mode = data->mode;
1128
1129 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
1130 if (!ks_pcie)
1131 return -ENOMEM;
1132
1133 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1134 if (!pci)
1135 return -ENOMEM;
1136
1137 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app");
1138 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
1139 if (IS_ERR(ks_pcie->va_app_base))
1140 return PTR_ERR(ks_pcie->va_app_base);
1141
1142 ks_pcie->app = *res;
1143
1144 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics");
1145 base = devm_pci_remap_cfg_resource(dev, res);
1146 if (IS_ERR(base))
1147 return PTR_ERR(base);
1148
1149 if (of_device_is_compatible(np, "ti,am654-pcie-rc"))
1150 ks_pcie->is_am6 = true;
1151
1152 pci->dbi_base = base;
1153 pci->dbi_base2 = base;
1154 pci->dev = dev;
1155 pci->ops = &ks_pcie_dw_pcie_ops;
1156 pci->version = version;
1157
1158 irq = platform_get_irq(pdev, 0);
1159 if (irq < 0)
1160 return irq;
1161
1162 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED,
1163 "ks-pcie-error-irq", ks_pcie);
1164 if (ret < 0) {
1165 dev_err(dev, "failed to request error IRQ %d\n",
1166 irq);
1167 return ret;
1168 }
1169
1170 ret = of_property_read_u32(np, "num-lanes", &num_lanes);
1171 if (ret)
1172 num_lanes = 1;
1173
1174 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL);
1175 if (!phy)
1176 return -ENOMEM;
1177
1178 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL);
1179 if (!link)
1180 return -ENOMEM;
1181
1182 for (i = 0; i < num_lanes; i++) {
1183 snprintf(name, sizeof(name), "pcie-phy%d", i);
1184 phy[i] = devm_phy_optional_get(dev, name);
1185 if (IS_ERR(phy[i])) {
1186 ret = PTR_ERR(phy[i]);
1187 goto err_link;
1188 }
1189
1190 if (!phy[i])
1191 continue;
1192
1193 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
1194 if (!link[i]) {
1195 ret = -EINVAL;
1196 goto err_link;
1197 }
1198 }
1199
1200 ks_pcie->np = np;
1201 ks_pcie->pci = pci;
1202 ks_pcie->link = link;
1203 ks_pcie->num_lanes = num_lanes;
1204 ks_pcie->phy = phy;
1205
1206 gpiod = devm_gpiod_get_optional(dev, "reset",
1207 GPIOD_OUT_LOW);
1208 if (IS_ERR(gpiod)) {
1209 ret = PTR_ERR(gpiod);
1210 if (ret != -EPROBE_DEFER)
1211 dev_err(dev, "Failed to get reset GPIO\n");
1212 goto err_link;
1213 }
1214
1215 /* Obtain references to the PHYs */
1216 for (i = 0; i < num_lanes; i++)
1217 phy_pm_runtime_get_sync(ks_pcie->phy[i]);
1218
1219 ret = ks_pcie_enable_phy(ks_pcie);
1220
1221 /* Release references to the PHYs */
1222 for (i = 0; i < num_lanes; i++)
1223 phy_pm_runtime_put_sync(ks_pcie->phy[i]);
1224
1225 if (ret) {
1226 dev_err(dev, "failed to enable phy\n");
1227 goto err_link;
1228 }
1229
1230 platform_set_drvdata(pdev, ks_pcie);
1231 pm_runtime_enable(dev);
1232 ret = pm_runtime_get_sync(dev);
1233 if (ret < 0) {
1234 dev_err(dev, "pm_runtime_get_sync failed\n");
1235 goto err_get_sync;
1236 }
1237
1238 if (dw_pcie_ver_is_ge(pci, 480A))
1239 ret = ks_pcie_am654_set_mode(dev, mode);
1240 else
1241 ret = ks_pcie_set_mode(dev);
1242 if (ret < 0)
1243 goto err_get_sync;
1244
1245 switch (mode) {
1246 case DW_PCIE_RC_TYPE:
1247 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) {
1248 ret = -ENODEV;
1249 goto err_get_sync;
1250 }
1251
1252 ret = of_property_read_u32(np, "num-viewport", &num_viewport);
1253 if (ret < 0) {
1254 dev_err(dev, "unable to read *num-viewport* property\n");
1255 goto err_get_sync;
1256 }
1257
1258 /*
1259 * "Power Sequencing and Reset Signal Timings" table in
1260 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0
1261 * indicates PERST# should be deasserted after minimum of 100us
1262 * once REFCLK is stable. The REFCLK to the connector in RC
1263 * mode is selected while enabling the PHY. So deassert PERST#
1264 * after 100 us.
1265 */
1266 if (gpiod) {
1267 usleep_range(100, 200);
1268 gpiod_set_value_cansleep(gpiod, 1);
1269 }
1270
1271 ks_pcie->num_viewport = num_viewport;
1272 pci->pp.ops = host_ops;
1273 ret = dw_pcie_host_init(&pci->pp);
1274 if (ret < 0)
1275 goto err_get_sync;
1276 break;
1277 case DW_PCIE_EP_TYPE:
1278 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) {
1279 ret = -ENODEV;
1280 goto err_get_sync;
1281 }
1282
1283 pci->ep.ops = ep_ops;
1284 ret = dw_pcie_ep_init(&pci->ep);
1285 if (ret < 0)
1286 goto err_get_sync;
1287 break;
1288 default:
1289 dev_err(dev, "INVALID device type %d\n", mode);
1290 }
1291
1292 ks_pcie_enable_error_irq(ks_pcie);
1293
1294 return 0;
1295
1296 err_get_sync:
1297 pm_runtime_put(dev);
1298 pm_runtime_disable(dev);
1299 ks_pcie_disable_phy(ks_pcie);
1300
1301 err_link:
1302 while (--i >= 0 && link[i])
1303 device_link_del(link[i]);
1304
1305 return ret;
1306 }
1307
ks_pcie_remove(struct platform_device * pdev)1308 static int ks_pcie_remove(struct platform_device *pdev)
1309 {
1310 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
1311 struct device_link **link = ks_pcie->link;
1312 int num_lanes = ks_pcie->num_lanes;
1313 struct device *dev = &pdev->dev;
1314
1315 pm_runtime_put(dev);
1316 pm_runtime_disable(dev);
1317 ks_pcie_disable_phy(ks_pcie);
1318 while (num_lanes--)
1319 device_link_del(link[num_lanes]);
1320
1321 return 0;
1322 }
1323
1324 static struct platform_driver ks_pcie_driver = {
1325 .probe = ks_pcie_probe,
1326 .remove = ks_pcie_remove,
1327 .driver = {
1328 .name = "keystone-pcie",
1329 .of_match_table = ks_pcie_of_match,
1330 },
1331 };
1332 builtin_platform_driver(ks_pcie_driver);
1333