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Searched refs:mrs1 (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h146 uint32_t mrs1; /* register content saved during training */ member
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_sdram_config.c223 .mrs1 = RW_MGR_MRS1,
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h157 u8 mrs1; member
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c1265 mrc_params->mrs1 = emrs1_cmd >> 6; in perform_jedec_init()
1680 dram_init_command(DCMD_MRS1(rk, mrc_params->mrs1)); in wr_level()
/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.c915 writel(rwcfg->mrs1, grpaddr); in rw_mgr_mem_load_user()