| /openbmc/linux/drivers/tty/serial/ |
| H A D | mcf.c | 202 unsigned char mr1, mr2; in mcf_set_termios() local
213 mr2 = 0; in mcf_set_termios()
246 mr2 |= MCFUART_MR2_STOP2; in mcf_set_termios()
248 mr2 |= MCFUART_MR2_STOP1; in mcf_set_termios()
252 mr2 |= MCFUART_MR2_TXCTS; in mcf_set_termios()
258 mr2 |= MCFUART_MR2_TXRTS; in mcf_set_termios()
266 writeb(mr2, port->membase + MCFUART_UMR); in mcf_set_termios()
419 unsigned char mr1, mr2; in mcf_config_rs485() local
423 mr2 = readb(port->membase + MCFUART_UMR); in mcf_config_rs485()
427 mr2 |= MCFUART_MR2_TXRTS; in mcf_config_rs485()
[all …]
|
| H A D | mpc52xx_uart.c | 115 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
148 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) in mpc52xx_psc_set_mode() argument
152 out_8(&PSC(port)->mode, mr2); in mpc52xx_psc_set_mode()
922 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) in mpc5125_psc_set_mode() argument
925 out_8(&PSC_5125(port)->mr2, mr2); in mpc5125_psc_set_mode()
1173 unsigned char mr1, mr2; in mpc52xx_uart_set_termios() local
1202 mr2 = 0; in mpc52xx_uart_set_termios()
1205 mr2 |= MPC52xx_PSC_MODE_TWO_STOP; in mpc52xx_uart_set_termios()
1207 mr2 |= ((new->c_cflag & CSIZE) == CS5) ? in mpc52xx_uart_set_termios()
1213 mr2 |= MPC52xx_PSC_MODE_TXCTS; in mpc52xx_uart_set_termios()
[all …]
|
| H A D | sccnxp.c | 642 u8 mr1, mr2; in sccnxp_set_termios() local
682 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; in sccnxp_set_termios()
687 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); in sccnxp_set_termios()
|
| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_k2g.c | 32 .mr2 = 0x00000000ul,
72 .mr2 = 0x00000000ul,
133 .mr2 = 0x00000008ul,
|
| H A D | ddr3_cfg.c | 30 .mr2 = 0x00000018ul,
|
| /openbmc/linux/drivers/ipack/devices/ |
| H A D | ipoctal.c | 503 unsigned char mr2 = 0; in ipoctal_set_termios() local
543 mr2 |= MR2_STOP_BITS_LENGTH_2; in ipoctal_set_termios()
545 mr2 |= MR2_STOP_BITS_LENGTH_1; in ipoctal_set_termios()
552 mr2 |= MR2_TxRTS_CONTROL_OFF | MR2_CTS_ENABLE_TX_ON; in ipoctal_set_termios()
555 mr2 |= MR2_TxRTS_CONTROL_OFF | MR2_CTS_ENABLE_TX_OFF; in ipoctal_set_termios()
560 mr2 |= MR2_TxRTS_CONTROL_OFF | MR2_CTS_ENABLE_TX_OFF; in ipoctal_set_termios()
564 mr2 |= MR2_TxRTS_CONTROL_ON | MR2_CTS_ENABLE_TX_OFF; in ipoctal_set_termios()
624 iowrite8(mr2, &channel->regs->w.mr); in ipoctal_set_termios()
|
| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 39 .mr2 = 16,
116 writel(dram_para.mr2, &mctl_phy->mr2); in mctl_init()
201 writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); in mctl_init()
|
| H A D | dram_sun8i_a83t.c | 136 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
141 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
|
| H A D | dram_sun8i_a33.c | 135 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
|
| H A D | dram_sun6i.c | 124 writel(MCTL_MR2, &mctl_phy->mr2); in mctl_channel_init()
|
| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 30 unsigned int mr2; member
|
| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | mpc52xx_psc.h | 155 u8 mr2; member
306 u8 mr2; /* PSC + 0x04 */ member
|
| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 26 u32 mr2; member
186 u32 mr2; /* 0x5c mode register 2 */ member
|
| H A D | dram_sun8i_a33.h | 76 u32 mr2; /* 0x38 */ member
|
| H A D | dram_sun8i_a83t.h | 76 u32 mr2; /* 0x38 */ member
|
| H A D | dram_sun9i.h | 109 u32 mr2; /* 0xa4 mode register 2 */ member
|
| H A D | dram_sun6i.h | 175 u32 mr2; /* 0x48 mode register 2 */ member
|
| /openbmc/linux/drivers/spi/ |
| H A D | spi-mpc512x-psc.c | 334 in_8(psc_addr(mps, mr2)); in mpc512x_psc_spi_prep_xfer_hw()
335 out_8(psc_addr(mps, mr2), 0x0); in mpc512x_psc_spi_prep_xfer_hw()
|
| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 139 u32 mr2; member
|
| H A D | stm32mp1_ddr_regs.h | 159 u32 mr2; /* 0x48 Mode 2*/ member
|
| H A D | stm32mp1_ddr.c | 148 DDRPHY_REG_TIMING(mr2),
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | sdram_elpida.c | 309 .mr2 = 0x4,
|
| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 36 debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2); in dump_phy_config()
355 spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | in init_ddr3param()
|
| H A D | ddr3.c | 54 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); in ddr3_init_ddrphy()
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 441 .mr2 = 0x6,
|