| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_k2g.c | 32 .mr2 = 0x00000000ul,
72 .mr2 = 0x00000000ul,
133 .mr2 = 0x00000008ul,
|
| H A D | ddr3_cfg.c | 30 .mr2 = 0x00000018ul,
|
| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 39 .mr2 = 16,
116 writel(dram_para.mr2, &mctl_phy->mr2); in mctl_init()
201 writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); in mctl_init()
|
| H A D | dram_sun8i_a83t.c | 136 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
141 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
|
| H A D | dram_sun8i_a33.c | 135 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
|
| H A D | dram_sun6i.c | 124 writel(MCTL_MR2, &mctl_phy->mr2); in mctl_channel_init()
|
| H A D | dram_sun9i.c | 634 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
|
| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 30 unsigned int mr2; member
|
| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 26 u32 mr2; member
186 u32 mr2; /* 0x5c mode register 2 */ member
|
| H A D | dram_sun8i_a33.h | 76 u32 mr2; /* 0x38 */ member
|
| H A D | dram_sun8i_a83t.h | 76 u32 mr2; /* 0x38 */ member
|
| H A D | dram_sun9i.h | 109 u32 mr2; /* 0xa4 mode register 2 */ member
|
| H A D | dram_sun6i.h | 175 u32 mr2; /* 0x48 mode register 2 */ member
|
| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 139 u32 mr2; member
|
| H A D | stm32mp1_ddr_regs.h | 159 u32 mr2; /* 0x48 Mode 2*/ member
|
| H A D | stm32mp1_ddr.c | 148 DDRPHY_REG_TIMING(mr2),
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | sdram_elpida.c | 309 .mr2 = 0x4,
|
| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 36 debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2); in dump_phy_config()
355 spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | in init_ddr3param()
|
| H A D | ddr3.c | 54 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); in ddr3_init_ddrphy()
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 441 .mr2 = 0x6,
|
| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | emif.h | 1245 s8 mr2; member
|
| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 120 set_mr(base, cs, mr_addr, mr_regs->mr2); in do_lpddr2_init()
|
| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | xtensa-modules.c.inc | 2752 { "mr2", 54, 1, 1,
4460 { { 38 /* mr2 */ }, 'i' }
4465 { { 38 /* mr2 */ }, 'o' }
4470 { { 38 /* mr2 */ }, 'm' }
|
| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | xtensa-modules.c.inc | 2834 { "mr2", FIELD__mr2, REGFILE_MR, 1,
|
| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | xtensa-modules.c.inc | 2931 { "mr2", FIELD__mr2, REGFILE_MR, 1,
|