| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_k2g.c | 30 .mr0 = 0x00001430ul,
70 .mr0 = 0x00001830ul,
131 .mr0 = 0x00001430ul,
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| H A D | ddr3_cfg.c | 28 .mr0 = 0x00001C70ul,
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| /openbmc/u-boot/arch/nds32/cpu/n1213/ |
| H A D | start.S | 124 mfsr $r1, $mr0
126 mtsr $r1, $mr0
137 mfsr $r1, $mr0
139 mtsr $r1, $mr0
148 mfsr $r1, $mr0
150 mtsr $r1, $mr0
155 mfsr $r1, $mr0
157 mtsr $r1, $mr0
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 37 .mr0 = 6736,
114 writel(dram_para.mr0, &mctl_phy->mr0); in mctl_init()
200 writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); in mctl_init()
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| H A D | dram_sun8i_a83t.c | 134 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
139 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
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| H A D | dram_sun8i_a33.c | 133 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
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| H A D | dram_sun6i.c | 122 writel(MCTL_MR0, &mctl_phy->mr0); in mctl_channel_init()
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| H A D | dram_sun9i.c | 632 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 28 unsigned int mr0; member
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| /openbmc/u-boot/board/imgtec/ci20/ |
| H A D | ci20.c | 286 .mr0 = 0x420,
330 .mr0 = 0x420,
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 24 u32 mr0; member
184 u32 mr0; /* 0x54 mode register 0 */ member
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| H A D | dram_sun8i_a33.h | 74 u32 mr0; /* 0x30 */ member
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| H A D | dram_sun8i_a83t.h | 74 u32 mr0; /* 0x30 */ member
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| H A D | dram_sun9i.h | 107 u32 mr0; /* 0x9c mode register 0 */ member
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| H A D | dram_sun6i.h | 173 u32 mr0; /* 0x40 mode register 0 */ member
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 137 u32 mr0; member
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| H A D | stm32mp1_ddr_regs.h | 157 u32 mr0; /* 0x40 Mode 0*/ member
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| H A D | stm32mp1_ddr.c | 146 DDRPHY_REG_TIMING(mr0),
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| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 34 debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0); in dump_phy_config()
346 spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 | in init_ddr3param()
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| H A D | ddr3.c | 52 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); in ddr3_init_ddrphy()
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| /openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 74 writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0); in ddr_phy_init()
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| /openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/ |
| H A D | jz4780_dram.h | 437 u16 mr0; /* Mode Register 0 */ member
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 92 mr0..mr3
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| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | xtensa-modules.c.inc | 2744 { "mr0", 52, 1, 1,
4430 { { 36 /* mr0 */ }, 'i' }
4435 { { 36 /* mr0 */ }, 'o' }
4440 { { 36 /* mr0 */ }, 'm' }
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| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | xtensa-modules.c.inc | 2826 { "mr0", FIELD__mr0, REGFILE_MR, 1,
|