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Searched refs:mop (Results 1 – 25 of 40) sorted by relevance

12

/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_fmemory.c.inc6 static void maybe_nanbox_load(TCGv freg, MemOp mop)
8 if ((mop & MO_SIZE) == MO_32) {
13 static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
22 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
23 maybe_nanbox_load(dest, mop);
29 static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
38 tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop);
43 static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
53 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
54 maybe_nanbox_load(dest, mop);
[all …]
H A Dtrans_memory.c.inc6 static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)
13 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
18 static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop)
25 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
29 static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop)
36 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
42 static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop)
49 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
54 static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
62 tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
[all …]
H A Dtrans_atomic.c.inc6 static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
12 tcg_gen_qemu_ld_i64(t1, t0, ctx->mem_idx, mop);
20 static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
40 val, ctx->mem_idx, mop);
50 MemOp mop)
66 func(dest, addr, val, ctx->mem_idx, mop);
H A Dtrans_vec.c.inc228 uint32_t oprsz, MemOp mop,
240 func(mop, vd_ofs, vj_ofs, vk_ofs, oprsz, ctx->vl / 8);
244 static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop,
248 return gvec_vvv_vl(ctx, a, 16, mop, func);
251 static bool gvec_xxx(DisasContext *ctx, arg_vvv *a, MemOp mop,
255 return gvec_vvv_vl(ctx, a, 32, mop, func);
259 uint32_t oprsz, MemOp mop,
270 func(mop, vd_ofs, vj_ofs, oprsz, ctx->vl / 8);
275 static bool gvec_vv(DisasContext *ctx, arg_vv *a, MemOp mop,
279 return gvec_vv_vl(ctx, a, 16, mop, func);
[all …]
/openbmc/qemu/accel/tcg/
H A Dtrace-events17 load_atom2_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
18 load_atom4_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
20 load_atom8_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
21 load_atom16_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
23 store_atom2_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
24 store_atom4_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
25 store_atom8_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
26 store_atom16_fallback(uint32_t memop, uintptr_t ra) "mop:0x%"PRIx32", ra:0x%"PRIxPTR""
H A Duser-exec.c984 MemOp mop, uintptr_t ra, MMUAccessType type) in cpu_mmu_lookup() argument
986 int a_bits = memop_alignment_bits(mop); in cpu_mmu_lookup()
1098 MemOp mop = get_memop(oi); in do_ld2_mmu() local
1101 haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type); in do_ld2_mmu()
1102 ret = load_atom_2(cpu, ra, haddr, mop); in do_ld2_mmu()
1105 if (mop & MO_BSWAP) { in do_ld2_mmu()
1116 MemOp mop = get_memop(oi); in do_ld4_mmu() local
1119 haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type); in do_ld4_mmu()
1120 ret = load_atom_4(cpu, ra, haddr, mop); in do_ld4_mmu()
1123 if (mop & MO_BSWAP) { in do_ld4_mmu()
[all …]
H A Dcputlb.c1817 MemOp mop = get_memop(oi); in atomic_mmu_lookup() local
1839 mop, size, false, retaddr); in atomic_mmu_lookup()
1865 if (!did_tlb_fill && (addr & ((1 << memop_alignment_bits(mop)) - 1))) { in atomic_mmu_lookup()
2164 MemOp mop, uintptr_t ra) in do_ld_beN() argument
2178 atom = mop & MO_ATOM_MASK; in do_ld_beN()
2185 tmp = mop & MO_SIZE; in do_ld_beN()
2213 uint64_t a, int mmu_idx, MemOp mop, uintptr_t ra) in do_ld16_beN() argument
2227 atom = mop & MO_ATOM_MASK; in do_ld16_beN()
2572 MemOp mop, uintptr_t ra) in do_st_leN() argument
2588 atom = mop & MO_ATOM_MASK; in do_st_leN()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a64.c335 bool is_write, MemOp mop) in check_lse2_align() argument
347 tcg_gen_addi_i32(tmp, tmp, memop_size(mop)); in check_lse2_align()
365 static MemOp check_atomic_align(DisasContext *s, int rn, MemOp mop) in check_atomic_align() argument
367 MemOp size = mop & MO_SIZE; in check_atomic_align()
370 return mop; in check_atomic_align()
383 check_lse2_align(s, rn, 0, true, mop); in check_atomic_align()
385 mop |= MO_ALIGN; in check_atomic_align()
387 return finalize_memop(s, mop); in check_atomic_align()
392 bool is_write, MemOp mop) in check_ordered_align() argument
394 MemOp size = mop & MO_SIZE; in check_ordered_align()
[all …]
H A Dtranslate-neon.c39 static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) in neon_load_element() argument
41 long offset = neon_element_offset(reg, ele, mop & MO_SIZE); in neon_load_element()
43 switch (mop) { in neon_load_element()
58 static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) in neon_load_element64() argument
60 long offset = neon_element_offset(reg, ele, mop & MO_SIZE); in neon_load_element64()
62 switch (mop) { in neon_load_element64()
470 MemOp mop, align, endian; in trans_VLDST_multiple() local
542 mop = endian | size | align; in trans_VLDST_multiple()
550 gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, mop); in trans_VLDST_multiple()
554 gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop); in trans_VLDST_multiple()
[all …]
H A Dtranslate.c4951 MemOp mop, int mem_idx) in op_load_rr() argument
4959 gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); in op_load_rr()
4960 disas_set_da_iss(s, mop, issinfo); in op_load_rr()
4972 MemOp mop, int mem_idx) in op_store_rr() argument
4988 gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); in op_store_rr()
4989 disas_set_da_iss(s, mop, issinfo); in op_store_rr()
5156 MemOp mop, int mem_idx) in op_load_ri() argument
5164 gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); in op_load_ri()
5165 disas_set_da_iss(s, mop, issinfo); in op_load_ri()
5177 MemOp mop, int mem_idx) in op_store_ri() argument
[all …]
/openbmc/qemu/tcg/
H A Dtcg-op-ldst.c442 static bool use_two_i64_for_i128(MemOp mop) in use_two_i64_for_i128() argument
453 switch (mop & MO_ATOM_MASK) { in use_two_i64_for_i128()
568 MemOp mop[2]; in tcg_gen_qemu_ld_i128_int() local
573 canonicalize_memop_i128_as_i64(mop, memop); in tcg_gen_qemu_ld_i128_int()
574 need_bswap = (mop[0] ^ memop) & MO_BSWAP; in tcg_gen_qemu_ld_i128_int()
589 gen_ld_i64(x, addr, make_memop_idx(mop[0], idx)); in tcg_gen_qemu_ld_i128_int()
605 gen_ld_i64(y, addr_p8, make_memop_idx(mop[1], idx)); in tcg_gen_qemu_ld_i128_int()
677 MemOp mop[2]; in tcg_gen_qemu_st_i128_int() local
681 canonicalize_memop_i128_as_i64(mop, memop); in tcg_gen_qemu_st_i128_int()
691 if ((mop[0] ^ memop) & MO_BSWAP) { in tcg_gen_qemu_st_i128_int()
[all …]
H A Dtci.c281 MemOp mop = get_memop(oi); in tci_qemu_ld() local
284 switch (mop & MO_SSIZE) { in tci_qemu_ld()
307 MemOp mop = get_memop(oi); in tci_qemu_st() local
310 switch (mop & MO_SIZE) { in tci_qemu_st()
/openbmc/qemu/target/mips/tcg/
H A Docteon_translate.c178 static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop) in trans_lx() argument
180 gen_lx(ctx, a->rd, a->base, a->index, mop); in trans_lx()
H A Dtranslate.h172 void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop);
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rva.c.inc33 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
42 tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
58 static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
75 ctx->mem_idx, mop);
H A Dtrans_rvzacas.c.inc65 static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a, MemOp mop)
80 tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop);
/openbmc/qemu/target/xtensa/
H A Dtranslate.c514 static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop, in gen_load_store_alignment() argument
517 if ((mop & MO_SIZE) == MO_8) { in gen_load_store_alignment()
518 return mop; in gen_load_store_alignment()
520 if ((mop & MO_AMASK) == MO_UNALN && in gen_load_store_alignment()
522 mop |= MO_ALIGN; in gen_load_store_alignment()
525 tcg_gen_andi_i32(addr, addr, ~0 << memop_alignment_bits(mop)); in gen_load_store_alignment()
527 return mop; in gen_load_store_alignment()
1625 MemOp mop; in translate_l32e() local
1628 mop = gen_load_store_alignment(dc, MO_TEUL, addr); in translate_l32e()
1629 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, mop); in translate_l32e()
[all …]
/openbmc/qemu/target/microblaze/
H A Dtranslate.c703 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, in do_load() argument
706 MemOp size = mop & MO_SIZE; in do_load()
708 mop |= mo_endian(dc); in do_load()
718 mop ^= MO_BSWAP; in do_load()
735 mop |= MO_ALIGN; in do_load()
739 tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); in do_load()
863 static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, in do_store() argument
866 MemOp size = mop & MO_SIZE; in do_store()
868 mop |= mo_endian(dc); in do_store()
878 mop ^= MO_BSWAP; in do_store()
[all …]
/openbmc/qemu/target/sparc/
H A Dldst_helper.c1159 MemOp mop = get_memop(oi); in helper_ld_code() local
1163 switch (mop & MO_SIZE) { in helper_ld_code()
1166 if (mop & MO_SIGN) { in helper_ld_code()
1172 if ((mop & MO_BSWAP) != MO_TE) { in helper_ld_code()
1175 if (mop & MO_SIGN) { in helper_ld_code()
1181 if ((mop & MO_BSWAP) != MO_TE) { in helper_ld_code()
1184 if (mop & MO_SIGN) { in helper_ld_code()
1190 if ((mop & MO_BSWAP) != MO_TE) { in helper_ld_code()
H A Dtranslate.c1784 TCGv_i32 asi, TCGv_i32 mop) in gen_helper_ld_asi() argument
1790 TCGv_i32 asi, TCGv_i32 mop) in gen_helper_st_asi() argument
1882 MemOp mop = MO_128 | MO_ATOM_IFALIGN_PAIR; in gen_st_asi() local
1889 tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop); in gen_st_asi()
1890 tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop); in gen_st_asi()
1893 tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop); in gen_st_asi()
1894 tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop); in gen_st_asi()
2209 MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16; in gen_ldda_asi() local
2212 tcg_gen_qemu_ld_i128(t, addr, da->mem_idx, mop); in gen_ldda_asi()
2218 if ((mop & MO_BSWAP) == MO_TE) { in gen_ldda_asi()
[all …]
/openbmc/qemu/target/loongarch/tcg/
H A Dtranslate.c42 static inline int vec_reg_offset(int regno, int index, MemOp mop) in vec_reg_offset() argument
44 const uint8_t size = 1 << mop; in vec_reg_offset()
/openbmc/qemu/target/riscv/
H A Dtranslate.c1131 MemOp mop) in gen_amo() argument
1135 MemOp size = mop & MO_SIZE; in gen_amo()
1138 mop |= MO_ATOM_WITHIN16; in gen_amo()
1140 mop |= MO_ALIGN; in gen_amo()
1145 func(dest, src1, src2, ctx->mem_idx, mop); in gen_amo()
1151 static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop) in gen_cmpxchg() argument
1158 tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); in gen_cmpxchg()
/openbmc/qemu/target/ppc/translate/
H A Dfixedpoint-impl.c.inc25 bool store, MemOp mop)
36 mop ^= ctx->default_tcg_memop_mask;
38 tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
40 tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
49 MemOp mop)
51 return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
55 bool store, MemOp mop)
61 return do_ldst_D(ctx, &d, update, store, mop);
65 bool store, MemOp mop)
67 return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
H A Dvsx-impl.c.inc1446 #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
2183 MemOp mop;
2188 mop = DEF_MEMOP(MO_128 | MO_ATOM_IFALIGN_PAIR);
2203 tcg_gen_qemu_st_i128(data, ea, ctx->mem_idx, mop);
2207 tcg_gen_qemu_st_i128(data, ea, ctx->mem_idx, mop);
2210 tcg_gen_qemu_ld_i128(data, ea, ctx->mem_idx, mop);
2214 tcg_gen_qemu_ld_i128(data, ea, ctx->mem_idx, mop);
2260 MemOp mop;
2269 mop = DEF_MEMOP(MO_UQ);
2276 tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
[all …]
/openbmc/qemu/target/hppa/
H A Dcpu.h378 int type, MemOp mop, hwaddr *pphys, int *pprot);

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