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Searched refs:mmVPG0_VPG_MEM_PWR (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h4775 #define mmVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_0_1_offset.h7748 #define mmVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_0_2_offset.h9357 #define mmVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_0_0_offset.h10493 #define mmVPG0_VPG_MEM_PWR … macro