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Searched refs:mmVGA_SRC_SPLIT_CNTL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h938 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h1139 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … macro
H A Ddcn_1_0_offset.h1585 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h1187 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h1111 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h1225 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h1125 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … macro