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Searched refs:mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h20 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h151 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h391 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h91 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h17 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h557 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro