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Searched refs:mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h28 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h159 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro
H A Ddcn_1_0_offset.h399 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h101 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h43 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h43 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h25 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h565 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … macro