Searched refs:mmVCE_UENC_DMA_DCLK_CTRL (Results 1 – 5 of 5) sorted by relevance
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/ |
H A D | vce_1_0_d.h | 54 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8250 macro
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H A D | vce_2_0_d.h | 49 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8390 macro
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H A D | vce_3_0_d.h | 54 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8390 macro
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | vce_v3_0.c | 201 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); in vce_v3_0_set_vce_sw_clock_gating() 206 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data); in vce_v3_0_set_vce_sw_clock_gating() 225 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); in vce_v3_0_set_vce_sw_clock_gating() 230 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data); in vce_v3_0_set_vce_sw_clock_gating()
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H A D | vce_v4_0.c | 873 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); 878 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); 897 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); 902 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);
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