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Searched refs:mmUVD_RB_SIZE2 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h41 #define mmUVD_RB_SIZE2 0x3c23 macro
H A Duvd_7_0_offset.h88 #define mmUVD_RB_SIZE2 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h210 #define mmUVD_RB_SIZE2 … macro
H A Dvcn_2_5_offset.h565 #define mmUVD_RB_SIZE2 … macro
H A Dvcn_2_0_0_offset.h922 #define mmUVD_RB_SIZE2 … macro
H A Dvcn_3_0_0_offset.h895 #define mmUVD_RB_SIZE2 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c1097 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_start()
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
H A Dvcn_v1_0.c956 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v1_0_start_spg_mode()
1256 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v1_0_pause_dpg_mode()
H A Dvcn_v2_5.c1149 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_start()
1499 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
H A Dvcn_v3_0.c1274 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_start()
1649 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
H A Duvd_v6_0.c874 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4); in uvd_v6_0_start()
H A Duvd_v7_0.c1125 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); in uvd_v7_0_start()