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Searched refs:mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h85 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h176 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h265 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h219 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_1_0_offset.h567 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h203 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h205 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h187 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h767 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro