| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_arcturus.c | 329 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)); in set_barrier_auto_waitcnt()
332 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG), data); in set_barrier_auto_waitcnt()
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| H A D | gfx_v7_0.c | 1960 WREG32(mmSQ_CONFIG, 1); in gfx_v7_0_constants_init()
1988 WREG32(mmSQ_CONFIG, 0); in gfx_v7_0_constants_init()
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| H A D | gfx_v8_0.c | 320 mmSQ_CONFIG, 0x07f80000, 0x01180000,
351 mmSQ_CONFIG, 0x07f80000, 0x01180000,
383 mmSQ_CONFIG, 0x07f80000, 0x07180000,
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| H A D | gfx_v9_0.c | 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
2372 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); in gfx_v9_0_init_sq_config()
2375 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); in gfx_v9_0_init_sq_config()
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| H A D | gfx_v10_0.c | 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
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| H A D | gfx_v6_0.c | 1738 WREG32(mmSQ_CONFIG, 0); in gfx_v6_0_constants_init()
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_d.h | 1413 #define mmSQ_CONFIG 0x2300 macro
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| H A D | gfx_7_2_d.h | 1806 #define mmSQ_CONFIG 0x2300 macro
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| H A D | gfx_7_0_d.h | 1785 #define mmSQ_CONFIG 0x2300 macro
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| H A D | gfx_8_0_d.h | 1999 #define mmSQ_CONFIG 0x2300 macro
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| H A D | gfx_8_1_d.h | 1967 #define mmSQ_CONFIG 0x2300 macro
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 393 #define mmSQ_CONFIG … macro
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| H A D | gc_9_2_1_offset.h | 383 #define mmSQ_CONFIG … macro
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| H A D | gc_9_1_offset.h | 387 #define mmSQ_CONFIG … macro
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| H A D | gc_10_1_0_offset.h | 2427 #define mmSQ_CONFIG … macro
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| H A D | gc_10_3_0_offset.h | 2516 #define mmSQ_CONFIG … macro
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