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Searched refs:mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h712 #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX … macro
H A Dgc_9_2_1_offset.h668 #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX … macro
H A Dgc_9_1_offset.h692 #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX … macro
H A Dgc_10_1_0_offset.h2616 #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX … macro
H A Dgc_10_3_0_offset.h2707 #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX … macro