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Searched refs:mmSDMA1_UTCL1_WR_STATUS_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_offset.h133 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 macro
H A Dsdma1_4_2_2_offset.h133 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX … macro
H A Dsdma1_4_2_offset.h133 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h1115 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX … macro
H A Dgc_10_3_0_offset.h1157 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX … macro