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Searched refs:mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h79 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro
H A Dsdma0_4_0_offset.h81 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 macro
H A Dsdma0_4_2_offset.h81 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro
H A Dsdma0_4_2_2_offset.h81 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h56 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro
H A Dgc_10_3_0_offset.h63 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro