Searched refs:mmSDMA0_RLC5_RB_WPTR_POLL_CNTL (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| H A D | sdma_v4_0.c | 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_2_offset.h | 808 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL … macro
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| H A D | sdma0_4_2_2_offset.h | 812 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL … macro
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 799 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL … macro
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| H A D | gc_10_3_0_offset.h | 822 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL … macro
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