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Searched refs:mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h432 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO … macro
H A Dsdma0_4_0_offset.h520 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 macro
H A Dsdma0_4_2_offset.h516 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO … macro
H A Dsdma0_4_2_2_offset.h520 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h249 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 macro
H A Doss_3_0_1_d.h298 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 macro
H A Doss_3_0_d.h417 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 macro
H A Doss_2_0_d.h298 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h510 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO … macro
H A Dgc_10_3_0_offset.h514 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO … macro