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Searched refs:mmSDMA0_PHASE2_QUANTUM (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_0_offset.h172 #define mmSDMA0_PHASE2_QUANTUM 0x004f macro
H A Dsdma0_4_2_offset.h172 #define mmSDMA0_PHASE2_QUANTUM … macro
H A Dsdma0_4_2_2_offset.h172 #define mmSDMA0_PHASE2_QUANTUM … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c446 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
H A Dsdma_v5_0.c635 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_0_ctx_switch_enable()
H A Dsdma_v4_0.c972 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); in sdma_v4_0_ctx_switch_enable()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h147 #define mmSDMA0_PHASE2_QUANTUM … macro
H A Dgc_10_3_0_offset.h144 #define mmSDMA0_PHASE2_QUANTUM … macro