Searched refs:mmRLC_CP_SCHEDULERS_Sienna_Cichlid (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mes_v10_1.c | 37 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 macro
1003 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); in mes_v10_1_kiq_setting()
1006 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in mes_v10_1_kiq_setting()
1008 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in mes_v10_1_kiq_setting()
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| H A D | gfx_v10_0.c | 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 macro
6313 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); in gfx_v10_0_kiq_setting()
6316 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in gfx_v10_0_kiq_setting()
6318 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in gfx_v10_0_kiq_setting()
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