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Searched refs:mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h39 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h128 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h215 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h167 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_1_0_offset.h481 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h151 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h153 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h135 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h673 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro