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Searched refs:mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h31 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h120 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h203 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
H A Ddcn_1_0_offset.h467 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h155 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h135 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h135 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h117 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h653 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … macro