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Searched refs:mmPA_SC_MODE_CNTL_1 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c77 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
133 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
316 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
354 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
403 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
H A Dgfx_v9_0.c614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h978 #define mmPA_SC_MODE_CNTL_1 0xA293 macro
H A Dgfx_7_2_d.h1031 #define mmPA_SC_MODE_CNTL_1 0xa293 macro
H A Dgfx_7_0_d.h1018 #define mmPA_SC_MODE_CNTL_1 0xa293 macro
H A Dgfx_8_0_d.h1113 #define mmPA_SC_MODE_CNTL_1 0xa293 macro
H A Dgfx_8_1_d.h1114 #define mmPA_SC_MODE_CNTL_1 0xa293 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h4091 #define mmPA_SC_MODE_CNTL_1 … macro
H A Dgc_9_2_1_offset.h4275 #define mmPA_SC_MODE_CNTL_1 … macro
H A Dgc_9_1_offset.h4321 #define mmPA_SC_MODE_CNTL_1 … macro
H A Dgc_10_1_0_offset.h6483 #define mmPA_SC_MODE_CNTL_1 … macro
H A Dgc_10_3_0_offset.h6114 #define mmPA_SC_MODE_CNTL_1 … macro