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Searched refs:mmPA_CL_ENHANCE (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c74 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
130 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
313 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
351 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
400 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
H A Dgfx_v10_0.c3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
H A Dgfx_v6_0.c1761 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | in gfx_v6_0_constants_init()
H A Dgfx_v7_0.c2001 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | in gfx_v7_0_constants_init()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h802 #define mmPA_CL_ENHANCE 0x2285 macro
H A Dgfx_7_2_d.h965 #define mmPA_CL_ENHANCE 0x2285 macro
H A Dgfx_7_0_d.h952 #define mmPA_CL_ENHANCE 0x2285 macro
H A Dgfx_8_1_d.h1047 #define mmPA_CL_ENHANCE 0x2285 macro
H A Dgfx_8_0_d.h1047 #define mmPA_CL_ENHANCE 0x2285 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h335 #define mmPA_CL_ENHANCE … macro
H A Dgc_9_1_offset.h331 #define mmPA_CL_ENHANCE … macro
H A Dgc_9_2_1_offset.h325 #define mmPA_CL_ENHANCE … macro
H A Dgc_10_1_0_offset.h2361 #define mmPA_CL_ENHANCE … macro
H A Dgc_10_3_0_offset.h2448 #define mmPA_CL_ENHANCE … macro