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Searched refs:mmOTG0_OTG_COUNT_CONTROL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h4785 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h4140 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h6553 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h6348 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h8006 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h7882 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h9037 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h8728 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … macro