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Searched refs:mmMPCC0_MPCC_SM_CONTROL (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h3579 #define mmMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_0_3_offset.h6102 #define mmMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_0_1_offset.h10252 #define mmMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_1_0_offset.h5369 #define mmMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_2_1_0_offset.h5606 #define mmMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_0_2_offset.h12476 #define mmMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_2_0_0_offset.h6544 #define mmMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_0_0_offset.h13761 #define mmMPCC0_MPCC_SM_CONTROL … macro