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Searched refs:mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h3596 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h6119 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h10269 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h5623 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h12493 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h6561 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h13778 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … macro