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Searched refs:mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h331 #define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX … macro
H A Dmp_10_0_offset.h331 #define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX … macro
H A Dmp_9_0_offset.h345 #define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 macro
H A Dmp_11_0_8_offset.h331 #define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX … macro
H A Dmp_11_0_offset.h335 #define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX … macro
H A Dmp_11_5_0_offset.h379 #define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX … macro