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Searched refs:mmMP1_SMN_C2PMSG_66 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c101 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu9_send_msg_to_smc_without_waiting()
H A Dsmu10_smumgr.c67 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu10_send_msg_to_smc_without_waiting()
H A Dvega20_smumgr.c94 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in vega20_send_msg_to_smc_without_waiting()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h250 #define mmMP1_SMN_C2PMSG_66 macro
H A Dmp_10_0_offset.h250 #define mmMP1_SMN_C2PMSG_66 macro
H A Dmp_9_0_offset.h262 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
H A Dmp_11_0_8_offset.h250 #define mmMP1_SMN_C2PMSG_66 macro
H A Dmp_11_0_offset.h252 #define mmMP1_SMN_C2PMSG_66 macro
H A Dmp_11_5_0_offset.h250 #define mmMP1_SMN_C2PMSG_66 macro
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_4_ppt.c46 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
1144 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); in smu_v13_0_4_set_smu_mailbox_registers()
H A Dsmu_v13_0.c64 #define mmMP1_SMN_C2PMSG_66 macro
2409 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); in smu_v13_0_set_smu_mailbox_registers()
H A Dsmu_v13_0_0_ppt.c73 #define mmMP1_SMN_C2PMSG_66 macro
2484 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); in smu_v13_0_0_set_smu_mailbox_registers()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c44 #define mmMP1_SMN_C2PMSG_66 macro
1476 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); in renoir_set_ppt_funcs()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c2194 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); in smu_v11_0_set_smu_mailbox_registers()