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Searched refs:mmMP1_SMN_C2PMSG_53 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h224 #define mmMP1_SMN_C2PMSG_53 … macro
H A Dmp_10_0_offset.h224 #define mmMP1_SMN_C2PMSG_53 … macro
H A Dmp_9_0_offset.h236 #define mmMP1_SMN_C2PMSG_53 0x0275 macro
H A Dmp_11_0_8_offset.h224 #define mmMP1_SMN_C2PMSG_53 … macro
H A Dmp_11_0_offset.h226 #define mmMP1_SMN_C2PMSG_53 … macro
H A Dmp_11_5_0_offset.h224 #define mmMP1_SMN_C2PMSG_53 … macro
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_0_ppt.c85 #define mmMP1_SMN_C2PMSG_53 … macro
2487 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); in smu_v13_0_0_set_smu_mailbox_registers()