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Searched refs:mmMMMC_VM_MX_L1_TLB_CNTL (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v2_3.c190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
201 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v2_3_init_tlb_regs()
386 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_gart_disable()
390 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v2_3_gart_disable()
H A Dmmhub_v2_0.c260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
271 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v2_0_init_tlb_regs()
454 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
458 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v2_0_gart_disable()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_0_0_offset.h1778 #define mmMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_2_3_0_offset.h1838 #define mmMMMC_VM_MX_L1_TLB_CNTL … macro