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Searched refs:mmMC_SEQ_WR_CTL_2 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h1001 #define mmMC_SEQ_WR_CTL_2 0x0AD5 macro
H A Dgmc_7_1_d.h645 #define mmMC_SEQ_WR_CTL_2 0xad5 macro
H A Dgmc_8_1_d.h749 #define mmMC_SEQ_WR_CTL_2 0xad5 macro
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c2455 case mmMC_SEQ_WR_CTL_2: in iceland_check_s0_mc_reg_index()
2635 …register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); in iceland_initialize_mc_reg_table()
H A Dtonga_smumgr.c2918 case mmMC_SEQ_WR_CTL_2: in tonga_check_s0_mc_reg_index()
3120 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); in tonga_initialize_mc_reg_table()
H A Dci_smumgr.c2528 case mmMC_SEQ_WR_CTL_2: in ci_check_s0_mc_reg_index()
2708 …register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); in ci_initialize_mc_reg_table()