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Searched refs:mmMC_SEQ_SUP_CNTL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v6_0.c168 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
173 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
174 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
187 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v6_0_mc_load_microcode()
188 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v6_0_mc_load_microcode()
H A Dgmc_v8_0.c305 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
309 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
310 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
322 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
323 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_tonga_mc_load_microcode()
324 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_tonga_mc_load_microcode()
384 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
385 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_polaris_mc_load_microcode()
392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
393 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_polaris_mc_load_microcode()
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H A Dgmc_v7_0.c196 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
213 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
214 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v7_0_mc_load_microcode()
215 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v7_0_mc_load_microcode()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h949 #define mmMC_SEQ_SUP_CNTL 0x0A32 macro
H A Dgmc_7_1_d.h784 #define mmMC_SEQ_SUP_CNTL 0xa32 macro
H A Dgmc_8_1_d.h888 #define mmMC_SEQ_SUP_CNTL 0xa32 macro