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Searched refs:mmGENFC_WT_1_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h100 #define mmGENFC_WT_1_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h81 #define mmGENFC_WT_1_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h81 #define mmGENFC_WT_1_BASE_IDX … macro
H A Ddcn_1_0_offset.h129 #define mmGENFC_WT_1_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h115 #define mmGENFC_WT_1_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h115 #define mmGENFC_WT_1_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h97 #define mmGENFC_WT_1_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h637 #define mmGENFC_WT_1_BASE_IDX … macro