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Searched refs:mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h1494 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h2608 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h3419 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_1_0_offset.h3573 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h3425 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h3964 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h4363 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h4011 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … macro