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Searched refs:mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h105 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h196 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h301 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_1_0_offset.h621 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h255 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h247 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h259 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h241 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … macro