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Searched refs:mmDP0_DP_SEC_CNTL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5523 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h5009 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h7979 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h9912 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
H A Ddcn_1_0_offset.h8408 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h9591 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h11005 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h10727 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h10259 #define mmDP0_DP_SEC_CNTL_BASE_IDX … macro