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Searched refs:mmDMA_CH_0_WR_COMP_ADDR_LO (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Ddma_ch_0_regs.h38 #define mmDMA_CH_0_WR_COMP_ADDR_LO 0x401020 macro
/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c3622 if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) { in goya_validate_wreg32()
4845 mmDMA_CH_0_WR_COMP_ADDR_LO; in goya_context_switch()
4855 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr)); in goya_context_switch()
4860 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id, in goya_context_switch()