Searched refs:mmDMA0_QM_GLBL_CFG0 (Results 1 – 3 of 3) sorted by relevance
22 #define mmDMA0_QM_GLBL_CFG0 0x508000 macro
408 [SP_DMA_CMDQ] = mmDMA0_QM_GLBL_CFG0,410 [SP_DMA_QUEUES_OFFSET] = mmDMA1_QM_GLBL_CFG0 - mmDMA0_QM_GLBL_CFG0,419 mmDMA0_QM_CP_FENCE0_CNT_0 - mmDMA0_QM_GLBL_CFG0,421 mmDMA0_QM_CP_FENCE0_RDATA_0 - mmDMA0_QM_GLBL_CFG0,422 [SP_CP_STS_OFFSET] = mmDMA0_QM_CP_STS_0 - mmDMA0_QM_GLBL_CFG0,2680 WREG32(mmDMA0_QM_GLBL_CFG0 + dma_qm_offset, enable_mask); in gaudi_enable_qman()3290 WREG32(mmDMA0_QM_GLBL_CFG0, 0); in gaudi_disable_pci_dma_qmans()
1512 pb_addr = (mmDMA0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; in gaudi_init_dma_protection_bits()1513 word_offset = ((mmDMA0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; in gaudi_init_dma_protection_bits()1514 mask = 1U << ((mmDMA0_QM_GLBL_CFG0 & 0x7F) >> 2); in gaudi_init_dma_protection_bits()