1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_
14 #define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_VDEC0_BRDG_CTRL
19  *   (Prototype: VDEC_BRDG_CTRL)
20  *****************************************
21  */
22 
23 #define mmDCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE 0x41E3100
24 
25 #define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_MASK 0x41E3104
26 
27 #define mmDCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x41E3108
28 
29 #define mmDCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x41E310C
30 
31 #define mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL 0x41E3110
32 
33 #define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x41E3114
34 
35 #define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR 0x41E3120
36 
37 #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x41E3124
38 
39 #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x41E3128
40 
41 #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x41E312C
42 
43 #define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x41E3130
44 
45 #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x41E3134
46 
47 #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x41E3138
48 
49 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x41E3160
50 
51 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x41E3170
52 
53 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x41E3180
54 
55 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x41E3190
56 
57 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x41E31A0
58 
59 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x41E31A4
60 
61 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x41E31B0
62 
63 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x41E31B4
64 
65 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x41E31C0
66 
67 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x41E31C4
68 
69 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x41E31D0
70 
71 #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x41E3200
72 
73 #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x41E3230
74 
75 #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x41E3260
76 
77 #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x41E3270
78 
79 #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x41E3280
80 
81 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x41E3290
82 
83 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x41E3294
84 
85 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x41E32A0
86 
87 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x41E32A4
88 
89 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x41E32B0
90 
91 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x41E32B4
92 
93 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x41E32C0
94 
95 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x41E32C4
96 
97 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x41E32D0
98 
99 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x41E3300
100 
101 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x41E3310
102 
103 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x41E3320
104 
105 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x41E3330
106 
107 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x41E3334
108 
109 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x41E3338
110 
111 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x41E3340
112 
113 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x41E3350
114 
115 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x41E3360
116 
117 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x41E3380
118 
119 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x41E3390
120 
121 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x41E3394
122 
123 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x41E33C0
124 
125 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x41E33D0
126 
127 #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x41E33E0
128 
129 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x41E3400
130 
131 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x41E3410
132 
133 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x41E3420
134 
135 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x41E3430
136 
137 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x41E3434
138 
139 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x41E3438
140 
141 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x41E3440
142 
143 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x41E3450
144 
145 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x41E3460
146 
147 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x41E3480
148 
149 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x41E3490
150 
151 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x41E3494
152 
153 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x41E34C0
154 
155 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x41E34D0
156 
157 #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x41E34E0
158 
159 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x41E3500
160 
161 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x41E3510
162 
163 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x41E3520
164 
165 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x41E3530
166 
167 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x41E3534
168 
169 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x41E3538
170 
171 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x41E3540
172 
173 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x41E3550
174 
175 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x41E3560
176 
177 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x41E3580
178 
179 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x41E3590
180 
181 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x41E3594
182 
183 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x41E35C0
184 
185 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x41E35D0
186 
187 #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x41E35E0
188 
189 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x41E3600
190 
191 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x41E3610
192 
193 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x41E3620
194 
195 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x41E3630
196 
197 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x41E3634
198 
199 #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x41E3638
200 
201 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x41E3640
202 
203 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x41E3650
204 
205 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x41E3660
206 
207 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x41E3680
208 
209 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x41E3690
210 
211 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x41E3694
212 
213 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x41E36C0
214 
215 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x41E36D0
216 
217 #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x41E36E0
218 
219 #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x41E3700
220 
221 #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x41E3704
222 
223 #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x41E3708
224 
225 #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x41E370C
226 
227 #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x41E3714
228 
229 #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x41E3718
230 
231 #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x41E371C
232 
233 #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x41E3720
234 
235 #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x41E3724
236 
237 #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x41E3728
238 
239 #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x41E372C
240 
241 #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x41E3730
242 
243 #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x41E3734
244 
245 #endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ */
246