Searched refs:mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 (Results 1 – 2 of 2) sorted by relevance
819 #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 0x411E650 macro
5238 WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, upper_32_bits(gaudi2->virt_msix_db_dma_addr)); in gaudi2_init_sm()10132 cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + offset; in gaudi2_restore_user_sm_registers()10137 size = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 - in gaudi2_restore_user_sm_registers()10149 cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + DCORE_OFFSET; in gaudi2_restore_user_sm_registers()10154 size = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 - mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0; in gaudi2_restore_user_sm_registers()