Searched refs:mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 (Results 1 – 2 of 2) sorted by relevance
179 #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 0x411E150 macro
5247 WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + (4 * i), in gaudi2_init_sm()10135 cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + offset; in gaudi2_restore_user_sm_registers()10152 cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + DCORE_OFFSET; in gaudi2_restore_user_sm_registers()