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Searched refs:mmDCCG_VSYNC_OTG5_LATCH_VALUE (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h144 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro
H A Ddcn_3_0_3_offset.h231 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro
H A Ddcn_3_0_1_offset.h344 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro
H A Ddcn_1_0_offset.h662 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro
H A Ddcn_2_1_0_offset.h300 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro
H A Ddcn_3_0_2_offset.h294 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro
H A Ddcn_2_0_0_offset.h310 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro
H A Ddcn_3_0_0_offset.h292 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … macro